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publication number s71gl064a_00 revision a amendment 2 issue date february 8, 2005 s71gl064a based mcps stacked multi-chip product (mcp) flash memory and ram 64 megabit (4 m x 16-bit) cmos 3.0 volt-only page mode flash memory and 16/8 megabit (1m/512k x 16-bit) pseudo static ram / static ram advance information notice to readers: the advance information st atus indicates that this document contains information on one or more products under development at spansion llc. the inform ation is intended to help you evaluate this product. do not design in this product without contacting the factory. spansion llc reserves the right to change or discont inue work on this proposed product without notice.
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this document states the current technical specifications regard ing the spansion product(s) described herein. each product desc ribed herein may be designated as ad- vance information, preliminary, or full production. see the section ?notice on data sheet designations? for definitions. publication number s71gl064a_00 revision a amendment 2 issue date february 8, 2005 distinctive characteristics mcp features ? power supply voltage of 2.7 to 3.1 volt ? high performance ? 100 ns access time (100 ns flash, 70 ns psram/ sram) ? 25 ns page read times ? packages ? 7 x 9 x 1.2 mm 56 ball fbga (tlc056) ? operating temperature ? ?25c to +85c ? ?40c to +85c general description the s71gl064a product series consists of s2 9gl064 flash memory with psram and sram combinations defined as: s71gl064a based mcps stacked multi-chip product (mcp) flash memory and ram 64 megabit (4 m x 16-bit) cmos 3.0 volt-only page mode flash memory and 16/8 megabit (1m/512k x 16-bit) pseudo static ram / static ram data sheet advance information flash memory density 64mb psram / sram density 8mb s71gl064a80/s71gl064a08 16mb s71gl064aa0/s71gl064a0a
2 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information notice on data sheet designations spansion llc issues data sheets with advance info rmation or preliminary designations to advise readers of product information or intended specif ications throughout the product life cycle, in - cluding development, qualification, initial production, and full production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their de - sign. the following descriptions of spansion data sheet designations are presented here to high - light their presence and definitions. advance information the advance information designation indicates that spansion llc is developing one or more spe - cific products, but has not committed any design to production. information presented in a doc - ument with this designation is likely to change, and in some ca ses, development on the product may discontinue. spansion llc therefore places the following conditions upon advance informa - tion content: ?this document contains information on one or more products under development at spansion llc. the information is intended to help you evaluate this product. do not design in this product without con- tacting the factory. spansion llc reserves the right to change or discontinue work on this proposed product without notice.? preliminary the preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. this designation covers several aspects of the prod - uct life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a pr eliminary document should be expected while keeping these as - pects of production under consideration. spansion places the following conditions upon prelimi - nary content: ?this document states the current technical specific ations regarding the spansion product(s) described herein. the preliminary status of this document indi cates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this document m ay be revised by subsequent versions or modifica- tions due to changes in technical specifications.? combination some data sheets will contain a combination of pr oducts with different designations (advance in - formation, preliminary, or full pr oduction). this type of document will distinguish these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with dc charac teristics table and ac erase and program table (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designation is removed from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option , temperature range, package type, or v io range. changes may also include those needed to clarify a descript ion or to correct a typographical error or incor - rect specification. spansion llc applies the follo wing conditions to docu ments in this category: ?this document states the current technical specific ations regarding the spansion product(s) described herein. spansion llc deems the produc ts to have been in sufficient production volume such that sub- sequent versions of this document are not expected to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur.? questions regarding these document designations may be directed to your local amd or fujitsu sales office.
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 3 advance information product selector guide 64 mb flash memory note: please see the valid combinations table for the model# description. device-model# (note) flash access time (ns) (p)sram density (p)sram access time (ns) (p)sram type package s71gl064a80-0k 100 8 m psram 70 psram1 tlc056 s71gl064a80-0p s71gl064a08-0b 8 m sram sram1 s71gl064a08-0f S71GL064AA0-0K 16 m psram psram1 s71gl064aa0-0p s71gl064aa0-0u psram7 s71gl064aa0-0z s71gl064a0a-0b 16 m sram sram1 s71gl064a0a-0f
4 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information s71gl064a based mcps distinctive characteristics . . . . . . . . . . . . . . . . . . . 1 mcp features ........................................................................................................ 1 general description . . . . . . . . . . . . . . . . . . . . . . . . 1 product selector guide . . . . . . . . . . . . . . . . . . . . . .3 64 mb flash memory ............................................................................................3 connection diagram (s71gl064a) . . . . . . . . . . . . .8 special handling instructions for fb ga package ...................................8 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ordering information . . . . . . . . . . . . . . . . . . . . . . . 10 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . 12 tlc056?56-ball fine-pitch ball grid array (fbga) 9 x 7 mm package ............................................................................................... 12 s29glxxxa mirrorbit? flash family distinctive characteristics 13 general description . . . . . . . . . . . . . . . . . . . . . . . . 14 product selector guide . . . . . . . . . . . . . . . . . . . . . 15 s29gl064a ............................................................................................................15 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 logic symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 device bus operations . . . . . . . . . . . . . . . . . . . . . . 19 table 1. device bus operations ........................................... 19 requirements for reading array data ......................................................... 19 page mode read ............................................................................................. 20 writing commands/command sequences ................................................ 20 write buffer .................................................................................................... 20 accelerated program operation ..... ......................................................... 20 autoselect functions ....................... .............................................................. 21 standby mode ....................................................................................................... 21 automatic sleep mode ...................................................................................... 21 reset#: hardware reset pin ........... .............................................................. 21 output disable mode ........................................................................................ 21 table 2. s29gl064a top boot sector architecture ................. 22 table 3. s29gl064a bottom boot sector architecture ............ 25 autoselect mode ................................................................................................ 29 table 4. autoselect codes, (high voltage method) ................ 30 sector group protection and unprot ection ............................................. 30 table 5. s29gl064a sector group protection/unprotection address ......................................... 31 figure 1. temporary sector group unprotect operation .......... 32 figure 2. in-system sector group protect/unprotect algorithms 33 secured silicon sector flash memory region ............................................34 write protect (wp#) ........................................................................................35 hardware data protection ............ ..................................................................35 low vcc write inhibit ................................................................................35 write pulse ?glitch? protection ................................................................35 logical inhibit ...................................................................................................35 power-up write inhibit ................................................................................36 common flash memory interface (cfi) . . . . . . 36 table 6. cfi query identification string ................................ 37 table 7. system interface string .......................................... 37 table 8. device geometry definition .................................... 38 table 9. primary vendor-specific extended query ................. 38 command definitions . . . . . . . . . . . . . . . . . . . . . .40 reading array data ........................................................................................... 40 reset command .................................................................................................40 autoselect command sequence ........... ......................................................... 41 enter secured silicon sect or/exit secured silicon sector command sequence ............................................................................. 41 word program command sequence .. ..................................................... 41 unlock bypass command sequence .... .................................................... 42 write buffer programming ................. ........................................................ 42 accelerated program .................................................................................... 44 figure 3. write buffer programming operation....................... 45 figure 4. program operation ............................................... 46 program suspend/program resume command sequence .................... 46 figure 5. program suspend/program resume ........................ 48 chip erase command sequence ...................................................................48 sector erase command sequence . . . . . . . . . . . 49 figure 6. erase operation ................................................... 50 erase suspend/erase resume command s .................................................. 50 table 10. command definiti ons (x16 mode, byte# = v ih ) ...... 52 dq7: data# polling ............................................................................................53 figure 7. data# polling algorithm ........................................ 54 ry/by#: ready/busy# ....................................................................................... 54 figure 8. toggle bit algorithm ............................................. 56 reading toggle bits dq6/dq2 ..................................................................... 57 dq5: exceeded timing limits ........................................................................ 57 dq3: sector erase timer ................................................................................ 58 dq1: write-to-buffer abort ............... ............................................................ 58 table 11. write operation status ......................................... 58 figure 9. maximum negative overshoot waveform................. 59 figure 10. maximum positive overshoot waveform ................ 59 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . 59 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 60 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 11. test setup ......................................................... 61 table 12. test specifications ............................................... 61 key to switching waveforms . . . . . . . . . . . . . . . . 62 figure 12. input waveforms and measurement levels ............ 62 read-only operations-s29gl064a on ly ................................................... 63 figure 13. read operation timings....................................... 63 figure 14. page read timings.............................................. 64 hardware reset (reset#) .............................................................................. 64 figure 15. reset timings .................................................... 65 erase and program operations-s29gl 064a only .................................. 66 figure 16. program operation timings .................................. 67 figure 17. accelerated program timing diagram .................... 67 figure 18. chip/sector erase operation timings..................... 68 figure 19. data# polling timings (during embedded algorithms)............................................ 69 figure 20. toggle bit timings (during embedded algorithms) .. 69 figure 21. dq2 vs. dq6 ...................................................... 70 temporary sector unprotect ............ ............................................................ 70 figure 22. temporary sector group unprotect timing diagram 70 figure 23. sector group protect and unprotect timing diagram 71 alternate ce# controlled erase and program operations-s29gl064a ................................................................. 72 figure 24. alternate ce# controlled write (erase/program) operation timings.............................................................. 73 erase and programming performance . . . . . . . . 74 psram type 1 functional description . . . . . . . . . . . . . . . . . . . . . 75 absolute maximum ratings . . . . . . . . . . . . . . . . . 75 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 76
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 5 advance information table 13. 4mb psram asynchronous .................................... 76 table 14. 8mb psram asynchronous .................................... 76 table 15. 16mb psram asynchronous .................................. 77 table 16. 16mb psram page mode ...................................... 78 table 17. 32mb psram page mode ...................................... 79 table 18. 64mb psram page mode ...................................... 79 timing test conditions . . . . . . . . . . . . . . . . . . . . 80 output load circuit .......................................................................................... 81 figure 25. output load circuit ............................................. 81 power up sequence . . . . . . . . . . . . . . . . . . . . . . . 81 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . .82 table 19. 4mb psram page mode ........................................ 82 table 20. 8mb psram asynchronous .................................... 84 figure 26. 16mb psram asynchronous.................................. 86 table 21. 16mb psram page mode ...................................... 87 table 22. 32mb psram page mode ...................................... 89 table 23. 64mb psram page mode ...................................... 91 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 92 read cycle ........................................................................................................... 92 figure 27. timing of read cycle (ce# = oe# = v il , we# = zz# = v ih )................................. 92 figure 28. timing waveform of read cycle (we# = zz# = v ih ) 93 figure 29. timing waveform of page mode read cycle (we# = zz# = v ih ) ........................................... 94 write cycle ..........................................................................................................95 figure 30. timing waveform of write cycle (we# control, zz# = v ih ) .................................................. 95 figure 31. timing waveform of write cycle (ce# control, zz# = v ih ) ................................................... 95 figure 32. timing wavefo rm of page mode write cycle (zz# = v ih ).............................................................. 96 power savings modes . . . . . . . . . . . . . . . . . . . . . . 96 partial array self refr esh (par) .................................................................... 96 temperature compensated refresh (f or 64mb) ......................................97 deep sleep mode ................................................................................................97 reduced memory size (for 32m and 16m) ...................................................97 other mode register settings (for 64m) .....................................................97 figure 33. mode register..................................................... 98 figure 34. mode register updatetimings (ub#, lb#, oe# are don?t care)................................................................................ 98 figure 35. deep sleep mode - entry/exit timings (for 64m) ..... 99 figure 36. deep sleep mo de - entry/exit timings (for 32m and 16m) ............................................................. 99 table 24. mode register update and deep sleep timings ....... 99 table 25. address patterns for pasr (a4=1) (64m) ............... 99 icc characteristics ..........................................................................................100 table 26. deep icc characteristics (for 64mb) .....................100 table 27. address patterns for par (a3= 0, a4=1) (32m) ......100 table 28. address patterns for rm s (a3 = 1, a4 = 1) (32m) ..100 table 29. low power icc characteristics (32m) ....................101 table 30. address patterns for par (a3= 0, a4=1) (16m) ......101 table 31. address patterns for rm s (a3 = 1, a4 = 1) (16m) ..101 table 32. low power icc characteristics (16m) ....................101 psram type 7 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . 102 functional description . . . . . . . . . . . . . . . . . . . . . 103 power down (for 32m, 64m only) . . . . . . . . . . . . 103 power down ...................................................................................................... 103 power down program sequence .................................................................104 address key .......................................................................................................104 absolute maximum ratings . . . . . . . . . . . . . . . . 105 recommended operating conditions . . . . . . . . 105 package capacitance . . . . . . . . . . . . . . . . . . . . . 105 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . 106 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . .107 read operation .................................................................................................107 write operation .............................................................................................. 108 power down parameters ...............................................................................109 other timing parameters ...............................................................................109 ac test conditions ..........................................................................................110 ac measurement output load circuits ....................................................110 figure 37. ac output load circuit ? 16 mb .......................... 110 figure 38. ac output load circuit ? 32 mb and 64 mb .......... 110 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 111 read timings .........................................................................................................111 figure 39. read timing #1 (basic timing)........................... 111 figure 40. read timing #2 (oe# address access ................. 111 figure 41. read timing #3 (lb#/ub# byte access).............. 112 figure 42. read timing #4 (page address access after ce1# control access for 32m and 64m only)........................................... 112 figure 43. read timing #5 (ran dom and page ad dress access for 32m and 64m only).......................................................... 113 write timings ..................................................................................................... 113 figure 44. write timing #1 (basic timing) .......................... 113 figure 45. write timing #2 (we# control) .......................... 114 figure 46. write timing #3-1 (we#/lb#/ub# byte write control)................................... 114 figure 47. write timing #3-3 (we#/lb#/ub# byte write control)................................... 115 figure 48. write timing #3-4 (we#/lb#/ub# byte write control)................................... 115 read/write timings ..........................................................................................116 figure 49. read/write timing #1-1 (ce1# control) .............. 116 figure 50. read / write timing #1-2 (ce1#/we#/oe# control) ................................................ 116 figure 51. read / write timing #2 (oe#, we# control)........ 117 figure 52. read / write timing #3 (oe#, we#, lb#, ub# control)......................................... 117 figure 53. power-up timing #1 ......................................... 118 figure 54. power-up timing #2 ......................................... 118 figure 55. power down entry and exit timing...................... 118 figure 56. standby entry timing after read or write ............ 119 figure 57. power down program timing (for 32m/64m only) . 119 type 1 sram common features . . . . . . . . . . . . . . . . . . . . . . . 120 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . 120 functional description . . . . . . . . . . . . . . . . . . . . 121 4m version f, 4m version g, 8m ve rsion c ..........................................121 byte mode ............................................................................................................121 8m version d .................................................................................................122 absolute maximum ratings . . . . . . . . . . . . . . . . 122 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . 123 capacitance ......................................................................................................... 123 dc operating characteristics . . . . . . . . . . . . . . 123 ac operating conditions . . . . . . . . . . . . . . . . . . .126 test conditions .................................................................................................126 figure 58. ac output load ................................................ 126 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . 126 table 33. read/write characteristics (v cc =2.7-3.3v) ........... 126 data retention characteristics . . . . . . . . . . . . . 127
6 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 59. timing waveform of re ad cycle(1) (address controlled, cs#1=oe#=v il , cs2=we#=v ih , ub# and/or lb#=v il )....... 128 figure 60. timing waveform of read cycle(2) (we#=v ih , if byte# is low, ignore ub#/lb# timing) ........................................ 129 figure 61. timing waveform of write cycle(1) (we# controlled, if byte# is low, ignore ub#/lb# timing).............................. 129 figure 62. timing waveform of wr ite cycle(2) (cs# controlled, if byte# is low, ignore ub#/lb# timing) ............................. 130 figure 63. timing waveform of write cycle(3) (ub#, lb# controlled) ...................................................................... 130 figure 64. data retention waveform .................................. 131 revision summary
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 7 advance information mcp block diagram v ss reset# flash io 15 -io 0 v cc f dq 15 to dq 0 ry/by# wp#/acc v cc v cc ce1#f flash-only address shared address oe# we# v ccs v cc ce1#s ub# lb# ce# ub# lb# psram/sram ce2s
8 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information connection diagram (s71gl064a) notes: 1. may be shared depending on density. ? a19 is shared for the 16m psram and above configurations. ? a18 is shared for the 8m (p )sram and above configurations. special handling instructions for fbga package special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultrasonic cleaning methods. the package and/or data integrity ma y be compromised if the package body is ex- posed to temperatures above 150 c for prolonged periods of time. mcp flash-only addresses shared addresses s71gl064aa0 a21-a20 a19-a0 s71gl064a0a a21-a20 a19-a0 s71gl064a80 a21-a19 a18-a0 s71gl064a08 a21-a19 a18-a0 c3 ub# d3 a18 e3 a17 f3 dq1 g3 dq9 h3 dq10 dq2 b3 lb# c5 ce2s a20 g5 dq4 h5 vccs rfu b5 we# c6 a19 d6 a9 e6 a10 f6 dq6 g6 dq13 h6 dq12 dq5 b6 a8 c4 rst#f ry/by# g4 dq3 h4 vccf dq11 b4 wp/acc c7 a12 d7 a13 e7 a14 f7 rfu g7 dq15 h7 dq7 dq14 b7 a11 c8 a15 d8 a21 e8 rfu f8 a16 g8 rfu vss c2 a6 d2 a5 e2 a4 f2 vss g2 oe# h2 dq0 ce1#s dq8 b2 a7 c1 a3 d1 a2 e1 a1 f1 a0 g1 ce1#f f5 f4 b1 b8 a3 a5 a6 a4 a7 a2 ram only shared (note 1) flash only legend reserved fo r future use 56-ball fine-pitch ball grid array (top view, balls facing down)
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 9 advance information pin description a21?a0 = 22 address inputs (common and flash only) dq15?dq0 = 16 data inputs/outputs (common) ce1#f = chip enable (flash) ce1#s = chip enable 1 (psram/sram) ce2s = chip enable 2 (psram/sram) oe# = output enable (common) we# = write enable (common) ry/by# = ready/busy output (flash 1) ub# = upper byte control (psram/sram) lb# = lower byte co ntrol (psram/sram) reset# = hardware reset pin, active low (flash) wp#/acc = hardware write protect/acceleration pin (flash) v cc f = flash 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v ccs = psram/sram power supply v ss = device ground (common) nc = pin not connected internally logic symbol 22 16 dq15?dq0 a21?a0 ce1#f oe# we # reset# r y/by# wp#/acc ub# ce2s ce1#s lb#
10 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information ordering information the order number is formed by a va lid combinations of the following: table 1: s71gl 064 a a0 ba w 9 z 0 packing type 0=tray 2 = 7? tape and reel 3 = 13? tape and reel model number see the valid combinations table. package modifier 0 = 7 x 9 mm, 1.2 mm height, 56 balls (tlc056) temperature range w=wireless (-25 c to +85 c) i = industrial (-40 c to +85 c) package type ba = fine-pitch bga lead (pb)-free compliant package bf = fine-pitch bga lead (pb)-free package psram / sram density 0a = 16 mb sram a0 = 16 mb psram 80 = 8 mb psram 08 = 8 mb sram process technology a = 200 nm, mirrorbit technology flash density 064 = 64mb product family s71gl multi-chip product (mcp) 3.0-volt page mode flash memory and ram
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 11 advance information s71gl064a valid combinations speed options (ns)/boot sector option (p)sram type/ access time (ns) package marking base ordering part number package & te m p e r a t u r e package modifier/model number packing type s71gl064a80 baw 0k 0, 2, 3 (note 1) 100 / bottom boot sector psram1/ 70 tlc056 s71gl064a80 0p 100 / top boot sector s71gl064a08 0b 100 / bottom boot sector sram1 / 70 s71gl064a08 0f 100 / top boot sector s71gl064aa0 0k 100 / bottom boot sector psram1/ 70 s71gl064aa0 0p 100 / top boot sector s71gl064aa0 0u 100 / bottom boot sector psram7 / 70 s71gl064aa0 0z 100 / top boot sector s71gl064a0a 0b 100 / bottom boot sector sram1 / 70 s71gl064a0a 0f 100 / top boot sector s71gl064a80 bfw 0k 0, 2, 3 (note 1) 100 / bottom boot sector psram1/ 70 s71gl064a80 0p 100 / top boot sector s71gl064a08 0b 100 / bottom boot sector sram1 / 70 s71gl064a08 0f 100 / top boot sector s71gl064aa0 0k 100 / bottom boot sector psram1/ 70 s71gl064aa0 0p 100 / top boot sector s71gl064aa0 0u 100 / bottom boot sector psram7 / 70 s71gl064aa0 0z 100 / top boot sector s71gl064a0a 0b 100 / bottom boot sector sram1 / 70 s71gl064a0a 0f 100 / top boot sector s71gl064a80 bai 0k 0, 2, 3 (note 1) 100 / bottom boot sector psram1/ 70 s71gl064a80 0p 100 / top boot sector s71gl064a08 0b 100 / bottom boot sector sram1 / 70 s71gl064a08 0f 100 / top boot sector s71gl064aa0 0k 100 / bottom boot sector psram1/ 70 s71gl064aa0 0p 100 / top boot sector s71gl064aa0 0u 100 / bottom boot sector psram7 / 70 s71gl064aa0 0z 100 / top boot sector s71gl064a0a 0b 100 / bottom boot sector sram1 / 70 s71gl064a0a 0f 100 / top boot sector s71gl064a80 bfi 0k 0, 2, 3 (note 1) 100 / bottom boot sector psram1/ 70 s71gl064a80 0p 100 / top boot sector s71gl064a08 0b 100 / bottom boot sector sram1 / 70 s71gl064a08 0f 100 / top boot sector s71gl064aa0 0k 100 / bottom boot sector psram1/ 70 s71gl064aa0 0p 100 / top boot sector s71gl064aa0 0u 100 / bottom boot sector psram7 / 70 s71gl064aa0 0z 100 / top boot sector s71gl064a0a 0b 100 / bottom boot sector sram1 / 70 s71gl064a0a 0f 100 / top boot sector notes: 1. type 0 is standard. specify other options as required. valid combinations valid combinations list configurations planned to be supported in volume for this de- vice. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
12 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information physical dimensions tlc056?56-ball fine-pitch ball grid array (fbga) 9 x 7 mm package 3348 \ 16-038.22a package tlc 056 jedec n/a d x e 9.00 mm x 7.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.20 --- --- ball height a2 0.81 --- 0.97 body thickness d 9.00 bsc. body size e 7.00 bsc. body size d1 5.60 bsc. matrix footprint e1 5.60 bsc. matrix footprint md 8 matrix size d direction me 8 matrix size e direction n 56 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a1,a8,d4,d5,e4,e5,h1,h8 depopulated solder balls notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. e1 7 se a d1 ed dc e f g h 8 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd bottom view c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 56x a1 a2 a 0.15 m m c c ab 0.08 pin a1
this document contains information on one or more products under development at spansion llc. the information is intended to he lp you evaluate this product. do not design in this product without contacting th e factory. spansion llc reserv es the right to change or discontinue work on this pr oposed product without notice. publication number s71gl064a_00 revision a amendment 2 issue date february 8, 2005 distinctive characteristics architectural advantages ? single power supply operation ? 3 volt read, erase, and program operations ? manufactured on 200 nm mirrorbit process technology ? secured silicon sector region ? 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random electronic serial numb er, accessible through a command sequence ? may be programmed and lock ed at the factory or by the customer ? flexible sector architecture ? 64mb (uniform sector models): 128 32 kword (64 kb) sectors or 128 32 kword sectors ? 64mb (boot sector mode ls): 127 32 kword (64 kb) sectors + 8 4kword (8kb) boot sectors ? compatibility with jedec standards ? provides pinout and software compatibility for single- power supply flash, and superior inadvertent write protection ? 100,000 erase cycles typical per sector ? 20-year data retention typical performance characteristics ? high performance ? 100 ns access time ? 4-word/8-byte page read buffer ? 25 ns page read times ? 16-word/32-byte write buffer, which reduces overall programming time for mu ltiple-word updates ? low power consumption (typical values at 3.0 v, 5 mhz) ? 18 ma typical active read current ? 50 ma typical erase/program current ? 1 a typical standby mode current software & hardware features ? software features ? program suspend & resume: read other sectors before programming operation is completed ? erase suspend & resume: read/program other sectors before an erase operation is completed ? data# polling & toggle bits provide status ? cfi (common flash interface) compliant: allows host system to identify and accommodate multiple flash devices ? unlock bypass program command reduces overall multiple-word programming time hardware features ? sector group protection: hardware-level method of preventing write operations within a sector group ? temporary sector unprotect: vid-level method of charging code in locked sectors ? wp#/acc input accelerates programming time (when high voltage is applied) fo r greater throughput during system production. protects first or last sector regardless of sector protection settings on uniform sector models ? hardware reset input (reset#) resets device ? ready/busy# output (ry/by#) detects program or erase cycle completiondistinctive characteristics s29glxxxa mirrorbit? flash family stacked multi-chip product (mcp) flash memory and ram 64 megabit (4 m x 16-bit) cmos 3.0 volt-only page mode flash memory and 16/8 megabit (1m/512k x 16-bit) pseudo static ram / static ram data sheet advance information
14 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information general description the s29gl064a is a 64 mb, organized as 4,194,304 words or 8,388,608 bytes. access times as fast as 90 ns are available. no te that each access time has a specific operat- ing voltage range (vcc) as specified in the product selector guide section. each device has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. each device requires only a single 3.0 volt power supply for both read and write functions. in addition to a vcc input, a high-voltage accelerated program (acc) feature provides shorter programming times through increased curre nt on the wp#/acc input. this feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. the device is entirely command set compatible with the jedec single-power-supply flash standard . commands are written to the device usin g standard microprocessor write timing. write cycles also internally latch addresses and data needed for the programming and erase operations. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data conten ts of other sectors. the device is fully erased when shipped from the factory. device programming and erasure are initiated through command sequences. once a program or erase operation has begun, the host system n eed only poll the dq7 (data# polling) or dq6 (toggle) status bits or monitor the ready/busy# (ry/by#) output to determine whether the operation is complete. to facilitate programming, an unlock bypass mode reduces com- mand sequence overhead by requiring only two write cycles to program data instead of four. hardware data protection measures include a low vcc detect or that automati cally inhibits write operations during power transitions. the hardware sector protection feature disables both program and erase operations in any comb ination of sectors of memory. this can be achieved in-system or vi a programming equipment. the erase suspend/erase resume feature allows the host system to pause an erase op- eration in a given sector to read or program any other sector and then complete the erase operation. the program suspend/program resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation. the hardware reset# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the device, enabling the host system to read boot-up firmware from the flash memory device. the device reduces power consumption in the standby mode when it detects specific voltage levels on ce# and reset#, or when addresses have been stable for a specified period of time. the write protect (wp#) feature protects the first or last sector by asserting a logic low on the wp#/acc pin or wp# pin, depending on model number. the protected sector will still be protected even during accelerated programming. the secured silicon sector provides a 128-word/256-byte ar ea for code or data that can be permanently protected. once this sector is protected, no further changes within the sector can occur. spansion mirrorbit flash technology combines years of flash memory manufacturing experi- ence to produce the highest levels of quality, reliability and cost effectiveness. the device electrically erases all bits within a sector simu ltaneously via hot-hole as sisted erase. the data is programmed using hot electron injection.
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 15 advance information product selector guide s29gl064a part number s29gl064a speed option 100 max. access time (ns) 100 max. ce# access time (ns) 100 max. page access time (ns) 25 max. oe# access time (ns) 25
16 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information block diagram input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# wp#/acc ce# oe# stb stb dq15 ? dq0 (a-1) sector switches ry/by# reset# data latch y-gating cell matrix address latch a21?a0
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 17 advance information pin descriptions a21?a0 = 22 address inputs a20?a0 = 21 address inputs dq7?dq0 = 8 data inputs/outputs dq14?dq0 = 15 data inputs/outputs dq15/a-1 = dq15 (data input/outp ut, word mode), a-1 (lsb address input, byte mode) ce# = chip enable input oe# = output enable input we# = write enable input wp#/acc = hardware write protect input/programming acceleration input acc = acceleration input wp# = hardware write protect input reset# = hardware reset pin input ry/by# = ready/busy output v cc = 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v ss = device ground nc = pin not connected internally v io = output buffer power logic symbols s29gl064a (models r1, r2) 22 16 or 8 dq15?dq0 (a-1) a21?a0 ce# oe# we# reset# ry/by# wp#/acc byte# v io
18 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information s29gl064a (models r3, r4) s29gl064a (model r5) s29gl064a (model r6, r7) 22 16 or 8 dq15?dq0 (a-1) a21?a0 ce# oe# we# reset# ry/by# wp#/acc byte# 22 16 dq15?dq0 a21?a0 ce# oe# we# reset# ry/by# acc v io 22 16 dq15?dq0 a21?a0 ce# oe# we# reset# acc wp# v io
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 19 advance information device bus operations this section describes the requirements and use of the device bus operations, which are ini- tiated through the internal command register. the command register it self does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data info rmation needed to execute the command. the contents of the register serve as inputs to the internal stat e machine. the state mach ine outputs dictate the function of the device. ta b l e 1 lists the device bus operations , the inputs and control levels they require, and the resulting output. the fo llowing subsections describe each of these op- erations in further detail. ta b l e 1 . device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 11.5?12.5 v, v hh = 11.5?12.5 v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes: 1. addresses are amax:a0 in word mode; amax:a-1 in byte mode. sector addresses ar e amax:a15 in both modes. 2. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the ?sector group pr otection and unprotection? section. 3. if wp# = v il , the first or last sector remains protected (for uniform sector devices), and the two outer boot sectors are protected (for bo ot sector devices). if wp# = v ih , the first or last sector, or the two outer boot sector s will be protected or unprotected as determined by the method described in ?sector group protection and unprotection?. all sectors are unprotected when shipped from the factory (the secured silicon sector may be factory protec ted depending on version ordered.) 4. d in or d out as required by command sequence, data polling, or sector protect algorithm (see figure 2 ). requirements for reading array data to read array data from the outputs, the sy stem must drive the ce# and oe# pins to v il . ce# is the power control and selects the device . oe# is the output control and gates array data to the output pins. we# should remain at v ih . the internal state machine is set for reading arra y data upon device power-up, or after a hard- ware reset. this ensures that no spurious altera tion of the memory cont ent occurs during the power transition. no command is necessary in th is mode to obtain ar ray data. standard mi- croprocessor read cycles that assert valid a ddresses on the device address inputs produce operation ce# oe# we# reset# wp# acc addresses (note 1) dq0?dq15 read l l h h x x a in d out write (program/erase) l h l h (note 3) x a in (note 4) accelerated program l h l h (note 3) v hh a in (note 4) standby v cc 0.3 v x x v cc 0.3 v x h x high-z output disable l h h h x x x high-z reset x x x l x x x high-z sector group protect (note 2) l h l v id h x sa, a6 =l, a3=l, a2=l, a1=h, a0=l (note 4) sector group unprotect (note 2) l h l v id h x sa, a6=h, a3=l, a2=l, a1=h, a0=l (note 4) te mp o ra r y s e c t o r group unprotect x x x v id h x a in (note 4)
20 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information valid data on the device data outputs. the de vice remains enabled for read access until the command register contents are altered. see ?reading array data? for mo re information. refer to the ac read-only operations table for timing specifications and th e timing diagram. refer to the dc characteristics table for the active current specification on reading array data. page mode read the device is capable of fast page mode read and is compatible with the page mode mask rom read operation. this mode provides faster read access speed for random locations within a page. the page size of the device is 4 words/ 8 bytes. the appropriate page is selected by the higher address bits a(max)?a2. address bits a1?a0 in word mode (a1?a-1 in byte mode) determine the specific word within a page. this is an asynchronous operation; the micropro- cessor supplies the speci fic word location. the random or initial page access is equal to t acc or t ce and subsequent page read accesses (as long as the locations specified by the microp rocessor falls within that page) is equivalent to t pacc . when ce# is deasserted and reasserted for a subsequent access, the access time is t acc or t ce . fast page mode accesses are obtained by keeping the ?read-page addresses? con- stant and changing the ?intra-read page? addresses. writing commands/command sequences to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . the device features an unlock bypass mode to facilitate faster programming. once the de- vice enters the unlock bypass mode, only two write cycles are required to program a word, instead of four. the ?word program command se quence? section has details on programming data to the device using both standa rd and unlock bypass command sequences. an erase operation can erase one sector, multiple sectors, or the entire device. refer to the dc characteristics table for the ac tive current specification for the write mode. the ac characteristics section contains timing specification tables and timing diagrams for write operations. write buffer write buffer programming allows the system writ e to a maximum of 16 words/32 bytes in one programming operation. this results in faster effective programming ti me than the standard programming algorithms. see ?write buffer? for more information. accelerated program operation the device offers accelerated program operatio ns through the acc function. this is one of two functions provided by the wp#/acc or acc pin, depending on model number. this func- tion is primarily intended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this pin, the device automati cally enters the aforementioned un- lock bypass mode, temporarily unprotects any protected sector groups, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle program command sequence as requ ired by the unlock bypass mode. removing v hh from the wp#/acc or acc pin, depending on model number, returns the device to normal operation. note that the wp#/acc or acc pin must not be at v hh for operations other than accelerated programming, or device damage ma y result. wp# has an internal pullup; when unconnected, wp# is at v ih .
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 21 advance information autoselect functions if the system writes the autoselect command sequence, the device enters the autoselect mode. the system can then read autoselect code s from the internal register (which is sepa- rate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the ?autoselect mode? section on page 29 and ?autoselect command sequence? sec- tion on page 41 sections for more information. standby mode when the system is not reading or writing to th e device, it can place the device in the standby mode. in this mode, current consumption is gr eatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# pins are both held at v io 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v io 0.3 v, the device will be in the standby mode, but the standby current will be greater. the de vice requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. refer to the ?dc characteristics? section on page 60 for the standby current specification. automatic sleep mode the automatic sleep mode minimi zes flash device energy cons umption. the device automat- ically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard address access timings provide new data when addresses are ch anged. while in sleep mode, output data is latched and always available to the system. refer to the ?dc characteristics? section on page 60 for the automatic sleep mode current specification. reset#: hardware reset pin the reset# pin provides a hardware method of resetting the device to reading array data. when the reset# pin is driven low for at least a period of t rp , the device immediately termi- nates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another co mmand sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc5 ). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system rese t circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. refer to the ac characteristics tabl es for reset# parameters and to figure 15 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state.
22 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information ta b l e 2 . s29gl064a top boot sector architecture sector sector address a21?a12 sector size (kbs/kwords) (x8) address range (x16) address range sa0 0000000xxx 64/32 000000h?00ffffh 00000h?07fffh sa1 0000001xxx 64/32 010000h?01ffffh 08000h?0ffffh sa2 0000010xxx 64/32 020000h?02ffffh 10000h?17fffh sa3 0000011xxx 64/32 030000h?03ffffh 18000h?1ffffh sa4 0000100xxx 64/32 040000h?04ffffh 20000h?27fffh sa5 0000101xxx 64/32 050000h?05ffffh 28000h?2ffffh sa6 0000110xxx 64/32 060000h?06ffffh 30000h?37fffh sa7 0000111xxx 64/32 070000h?07ffffh 38000h?3ffffh sa8 0001000xxx 64/32 080000h?08ffffh 40000h?47fffh sa9 0001001xxx 64/32 090000h?09ffffh 48000h?4ffffh sa10 0001010xxx 64/32 0a0000h?0affffh 50000h?57fffh sa11 0001011xxx 64/32 0b0000h?0bffffh 58000h?5ffffh sa12 0001100xxx 64/32 0c0000h?0cffffh 60000h?67fffh sa13 0001101xxx 64/32 0d0000h?0dffffh 68000h?6ffffh sa14 0001101xxx 64/32 0e0000h?0effffh 70000h?77fffh sa15 0001111xxx 64/32 0f0000h?0fffffh 78000h?7ffffh sa16 0010000xxx 64/32 100000h?00ffffh 80000h?87fffh sa17 0010001xxx 64/32 110000h?11ffffh 88000h?8ffffh sa18 0010010xxx 64/32 120000h?12ffffh 90000h?97fffh sa19 0010011xxx 64/32 130000h?13ffffh 98000h?9ffffh sa20 0010100xxx 64/32 140000h?14ffffh a0000h?a7fffh sa21 0010101xxx 64/32 150000h?15ffffh a8000h?affffh sa22 0010110xxx 64/32 160000h?16ffffh b0000h?b7fffh sa23 0010111xxx 64/32 170000h?17ffffh b8000h?bffffh sa24 0011000xxx 64/32 180000h?18ffffh c0000h?c7fffh sa25 0011001xxx 64/32 190000h?19ffffh c8000h?cffffh sa26 0011010xxx 64/32 1a0000h?1affffh d0000h?d7fffh sa27 0011011xxx 64/32 1b0000h?1bffffh d8000h?dffffh sa28 0011000xxx 64/32 1c0000h?1cffffh e0000h?e7fffh sa29 0011101xxx 64/32 1d0000h?1dffffh e8000h?effffh sa30 0011110xxx 64/32 1e0000h?1effffh f0000h?f7fffh sa31 0011111xxx 64/32 1f0000h?1fffffh f8000h?fffffh sa32 0100000xxx 64/32 200000h?20ffffh f9000h?107fffh sa33 0100001xxx 64/32 210000h?21ffffh 108000h?10ffffh sa34 0100010xxx 64/32 220000h?22ffffh 110000h?117fffh sa35 0101011xxx 64/32 230000h?23ffffh 118000h?11ffffh
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 23 advance information sa36 0100100xxx 64/32 240000h?24ffffh 120000h?127fffh sa37 0100101xxx 64/32 250000h?25ffffh 128000h?12ffffh sa38 0100110xxx 64/32 260000h?26ffffh 130000h?137fffh sa39 0100111xxx 64/32 270000h?27ffffh 138000h?13ffffh sa40 0101000xxx 64/32 280000h?28ffffh 140000h?147fffh sa41 0101001xxx 64/32 290000h?29ffffh 148000h?14ffffh sa42 0101010xxx 64/32 2a0000h?2affffh 150000h?157fffh sa43 0101011xxx 64/32 2b0000h?2bffffh 158000h?15ffffh sa44 0101100xxx 64/32 2c0000h?2cffffh 160000h?167fffh sa45 0101101xxx 64/32 2d0000h?2dffffh 168000h?16ffffh sa46 0101110xxx 64/32 2e0000h?2effffh 170000h?177fffh sa47 0101111xxx 64/32 2f0000h?2fffffh 178000h?17ffffh sa48 0110000xxx 64/32 300000h?30ffffh 180000h?187fffh sa49 0110001xxx 64/32 310000h?31ffffh 188000h?18ffffh sa50 0110010xxx 64/32 320000h?32ffffh 190000h?197fffh sa51 0110011xxx 64/32 330000h?33ffffh 198000h?19ffffh sa52 0100100xxx 64/32 340000h?34ffffh 1a0000h?1a7fffh sa53 0110101xxx 64/32 350000h?35ffffh 1a8000h?1affffh sa54 0110110xxx 64/32 360000h?36ffffh 1b0000h?1b7fffh sa55 0110111xxx 64/32 370000h?37ffffh 1b8000h?1bffffh sa56 0111000xxx 64/32 380000h?38ffffh 1c0000h?1c7fffh sa57 0111001xxx 64/32 390000h?39ffffh 1c8000h?1cffffh sa58 0111010xxx 64/32 3a0000h?3affffh 1d0000h?1d7fffh sa59 0111011xxx 64/32 3b0000h?3bffffh 1d8000h?1dffffh sa60 0111100xxx 64/32 3c0000h?3cffffh 1e0000h?1e7fffh sa61 0111101xxx 64/32 3d0000h?3dffffh 1e8000h?1effffh sa62 0111110xxx 64/32 3e0000h?3effffh 1f0000h?1f7fffh sa63 0111111xxx 64/32 3f0000h?3fffffh 1f8000h?1fffffh sa64 1000000xxx 64/32 400000h?40ffffh 200000h?207fffh sa65 1000001xxx 64/32 410000h?41ffffh 208000h?20ffffh sa66 1000010xxx 64/32 420000h?42ffffh 210000h?217fffh sa67 1000011xxx 64/32 430000h?43ffffh 218000h?21ffffh sa68 1000100xxx 64/32 440000h?44ffffh 220000h?227fffh sa69 1000101xxx 64/32 450000h?45ffffh 228000h?22ffffh sa70 1000110xxx 64/32 460000h?46ffffh 230000h?237fffh sa71 1000111xxx 64/32 470000h?47ffffh 238000h?23ffffh table 2. s29gl064a top boot se ctor architecture (continued) sector sector address a21?a12 sector size (kbs/kwords) (x8) address range (x16) address range
24 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information sa72 1001000xxx 64/32 480000h?48ffffh 240000h?247fffh sa73 1001001xxx 64/32 490000h?49ffffh 248000h?24ffffh sa74 1001010xxx 64/32 4a0000h?4affffh 250000h?257fffh sa75 1001011xxx 64/32 4b0000h?4bffffh 258000h?25ffffh sa76 1001100xxx 64/32 4c0000h?4cffffh 260000h?267fffh sa77 1001101xxx 64/32 4d0000h?4dffffh 268000h?26ffffh sa78 1001110xxx 64/32 4e0000h?4effffh 270000h?277fffh sa79 1001111xxx 64/32 4f0000h?4fffffh 278000h?27ffffh sa80 1010000xxx 64/32 500000h?50ffffh 280000h?28ffffh sa81 1010001xxx 64/32 510000h?51ffffh 288000h?28ffffh sa82 1010010xxx 64/32 520000h?52ffffh 290000h?297fffh sa83 1010011xxx 64/32 530000h?53ffffh 298000h?29ffffh sa84 1010100xxx 64/32 540000h?54ffffh 2a0000h?2a7fffh sa85 1010101xxx 64/32 550000h?55ffffh 2a8000h?2affffh sa86 1010110xxx 64/32 560000h?56ffffh 2b0000h?2b7fffh sa87 1010111xxx 64/32 570000h?57ffffh 2b8000h?2bffffh sa88 1011000xxx 64/32 580000h?58ffffh 2c0000h?2c7fffh sa89 1011001xxx 64/32 590000h?59ffffh 2c8000h?2cffffh sa90 1011010xxx 64/32 5a0000h?5affffh 2d0000h?2d7fffh sa91 1011011xxx 64/32 5b0000h?5bffffh 2d8000h?2dffffh sa92 1011100xxx 64/32 5c0000h?5cffffh 2e0000h?2e7fffh sa93 1011101xxx 64/32 5d0000h?5dffffh 2e8000h?2effffh sa94 1011110xxx 64/32 5e0000h?5effffh 2f0000h?2fffffh sa95 1011111xxx 64/32 5f0000h?5fffffh 2f8000h?2fffffh sa96 1100000xxx 64/32 600000h?60ffffh 300000h?307fffh sa97 1100001xxx 64/32 610000h?61ffffh 308000h?30ffffh sa98 1100010xxx 64/32 620000h?62ffffh 310000h?317fffh sa99 1100011xxx 64/32 630000h?63ffffh 318000h?31ffffh sa100 1100100xxx 64/32 640000h?64ffffh 320000h?327fffh sa101 1100101xxx 64/32 650000h?65ffffh 328000h?32ffffh sa102 1100110xxx 64/32 660000h?66ffffh 330000h?337fffh sa103 1100111xxx 64/32 670000h?67ffffh 338000h?33ffffh sa104 1101000xxx 64/32 680000h?68ffffh 340000h?347fffh sa105 1101001xxx 64/32 690000h?69ffffh 348000h?34ffffh sa106 1101010xxx 64/32 6a0000h?6affffh 350000h?357fffh sa107 1101011xxx 64/32 6b0000h?6bffffh 358000h?35ffffh table 2. s29gl064a top boot se ctor architecture (continued) sector sector address a21?a12 sector size (kbs/kwords) (x8) address range (x16) address range
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 25 advance information sa108 1101100xxx 64/32 6c0000h?6cffffh 360000h?367fffh sa109 1101101xxx 64/32 6d0000h?6dffffh 368000h?36ffffh sa110 1101110xxx 64/32 6e0000h?6effffh 370000h?377fffh sa111 1101111xxx 64/32 6f0000h?6fffffh 378000h?37ffffh sa112 1110000xxx 64/32 700000h?70ffffh 380000h?387fffh sa113 1110001xxx 64/32 710000h?71ffffh 388000h?38ffffh sa114 1110010xxx 64/32 720000h?72ffffh 390000h?397fffh sa115 1110011xxx 64/32 730000h?73ffffh 398000h?39ffffh sa116 1110100xxx 64/32 740000h?74ffffh 3a0000h?3a7fffh sa117 1110101xxx 64/32 750000h?75ffffh 3a8000h?3affffh sa118 1110110xxx 64/32 760000h?76ffffh 3b0000h?3b7fffh sa119 1110111xxx 64/32 770000h?77ffffh 3b8000h?3bffffh sa120 1111000xxx 64/32 780000h?78ffffh 3c0000h?3c7fffh sa121 1111001xxx 64/32 790000h?79ffffh 3c8000h?3cffffh sa122 1111010xxx 64/32 7a0000h?7affffh 3d0000h?3d7fffh sa123 1111011xxx 64/32 7b0000h?7bffffh 3d8000h?3dffffh sa124 1111100xxx 64/32 7c0000h?7cffffh 3e0000h?3e7fffh sa125 1111101xxx 64/32 7d0000h?7dffffh 3e8000h?3effffh sa126 1111110xxx 64/32 7e0000h?7effffh 3f0000h?3f7fffh sa127 1111111000 8/4 7f0000h?7f1fffh 3f8000h?3f8fffh sa128 1111111001 8/4 7f2000h?7f3fffh 3f9000h?3f9fffh sa129 1111111010 8/4 7f4000h?7f5fffh 3fa000h?3fafffh sa130 1111111011 8/4 7f6000h?7f7fffh 3fb000h?3fbfffh sa131 1111111100 8/4 7f8000h?7f9fffh 3fc000h?3fcfffh sa132 1111111101 8/4 7fa000h?7fbfffh 3fd000h?3fdfffh sa133 1111111110 8/4 7fc000h?7fdfffh 3fe000h?3fefffh sa134 1111111111 8/4 7fe000h?7fffffh 3ff000h?3fffffh ta b l e 3 . s29gl064a bottom boot sector architecture sector sector address a21?a12 sector size (kbs/kwords) (x8) address range (x16) address range sa0 0000000000 8/4 000000h?001fffh 00000h?00fffh sa1 0000000001 8/4 002000h?003fffh 01000h?01fffh sa2 0000000010 8/4 004000h?005fffh 02000h?02fffh sa3 0000000011 8/4 006000h?007fffh 03000h?03fffh sa4 0000000100 8/4 008000h?009fffh 04000h?04fffh sa5 0000000101 8/4 00a000h?00bfffh 05000h?05fffh table 2. s29gl064a top boot se ctor architecture (continued) sector sector address a21?a12 sector size (kbs/kwords) (x8) address range (x16) address range
26 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information sa6 0000000110 8/4 00c000h?00dfffh 06000h?06fffh sa7 0000000111 8/4 00e000h?00fffffh 07000h?07fffh sa8 0000001xxx 64/32 010000h?01ffffh 08000h?0ffffh sa9 0000010xxx 64/32 020000h?02ffffh 10000h?17fffh sa10 0000011xxx 64/32 030000h?03ffffh 18000h?1ffffh sa11 0000100xxx 64/32 040000h?04ffffh 20000h?27fffh sa12 0000101xxx 64/32 050000h?05ffffh 28000h?2ffffh sa13 0000110xxx 64/32 060000h?06ffffh 30000h?37fffh sa14 0000111xxx 64/32 070000h?07ffffh 38000h?3ffffh sa15 0001000xxx 64/32 080000h?08ffffh 40000h?47fffh sa16 0001001xxx 64/32 090000h?09ffffh 48000h?4ffffh sa17 0001010xxx 64/32 0a0000h?0affffh 50000h?57fffh sa18 0001011xxx 64/32 0b0000h?0bffffh 58000h?5ffffh sa19 0001100xxx 64/32 0c0000h?0cffffh 60000h?67fffh sa20 0001101xxx 64/32 0d0000h?0dffffh 68000h?6ffffh sa21 0001101xxx 64/32 0e0000h?0effffh 70000h?77fffh sa22 0001111xxx 64/32 0f0000h?0fffffh 78000h?7ffffh sa23 0010000xxx 64/32 100000h?00ffffh 80000h?87fffh sa24 0010001xxx 64/32 110000h?11ffffh 88000h?8ffffh sa25 0010010xxx 64/32 120000h?12ffffh 90000h?97fffh sa26 0010011xxx 64/32 130000h?13ffffh 98000h?9ffffh sa27 0010100xxx 64/32 140000h?14ffffh a0000h?a7fffh sa28 0010101xxx 64/32 150000h?15ffffh a8000h?affffh sa29 0010110xxx 64/32 160000h?16ffffh b0000h?b7fffh sa30 0010111xxx 64/32 170000h?17ffffh b8000h?bffffh sa31 0011000xxx 64/32 180000h?18ffffh c0000h?c7fffh sa32 0011001xxx 64/32 190000h?19ffffh c8000h?cffffh sa33 0011010xxx 64/32 1a0000h?1affffh d0000h?d7fffh sa34 0011011xxx 64/32 1b0000h?1bffffh d8000h?dffffh sa35 0011000xxx 64/32 1c0000h?1cffffh e0000h?e7fffh sa36 0011101xxx 64/32 1d0000h?1dffffh e8000h?effffh sa37 0011110xxx 64/32 1e0000h?1effffh f0000h?f7fffh sa38 0011111xxx 64/32 1f0000h?1fffffh f8000h?fffffh sa39 0100000xxx 64/32 200000h?20ffffh f9000h?107fffh sa40 0100001xxx 64/32 210000h?21ffffh 108000h?10ffffh sa41 0100010xxx 64/32 220000h?22ffffh 110000h?117fffh table 3. s29gl064a bottom boot sector architecture (continued) sector sector address a21?a12 sector size (kbs/kwords) (x8) address range (x16) address range
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 27 advance information sa42 0101011xxx 64/32 230000h?23ffffh 118000h?11ffffh sa43 0100100xxx 64/32 240000h?24ffffh 120000h?127fffh sa44 0100101xxx 64/32 250000h?25ffffh 128000h?12ffffh sa45 0100110xxx 64/32 260000h?26ffffh 130000h?137fffh sa46 0100111xxx 64/32 270000h?27ffffh 138000h?13ffffh sa47 0101000xxx 64/32 280000h?28ffffh 140000h?147fffh sa48 0101001xxx 64/32 290000h?29ffffh 148000h?14ffffh sa49 0101010xxx 64/32 2a0000h?2affffh 150000h?157fffh sa50 0101011xxx 64/32 2b0000h?2bffffh 158000h?15ffffh sa51 0101100xxx 64/32 2c0000h?2cffffh 160000h?167fffh sa52 0101101xxx 64/32 2d0000h?2dffffh 168000h?16ffffh sa53 0101110xxx 64/32 2e0000h?2effffh 170000h?177fffh sa54 0101111xxx 64/32 2f0000h?2fffffh 178000h?17ffffh sa55 0110000xxx 64/32 300000h?30ffffh 180000h?187fffh sa56 0110001xxx 64/32 310000h?31ffffh 188000h?18ffffh sa57 0110010xxx 64/32 320000h?32ffffh 190000h?197fffh sa58 0110011xxx 64/32 330000h?33ffffh 198000h?19ffffh sa59 0100100xxx 64/32 340000h?34ffffh 1a0000h?1a7fffh sa60 0110101xxx 64/32 350000h?35ffffh 1a8000h?1affffh sa61 0110110xxx 64/32 360000h?36ffffh 1b0000h?1b7fffh sa62 0110111xxx 64/32 370000h?37ffffh 1b8000h?1bffffh sa63 0111000xxx 64/32 380000h?38ffffh 1c0000h?1c7fffh sa64 0111001xxx 64/32 390000h?39ffffh 1c8000h?1cffffh sa65 0111010xxx 64/32 3a0000h?3affffh 1d0000h?1d7fffh sa66 0111011xxx 64/32 3b0000h?3bffffh 1d8000h?1dffffh sa67 0111100xxx 64/32 3c0000h?3cffffh 1e0000h?1e7fffh sa68 0111101xxx 64/32 3d0000h?3dffffh 1e8000h?1effffh sa69 0111110xxx 64/32 3e0000h?3effffh 1f0000h?1f7fffh sa70 0111111xxx 64/32 3f0000h?3fffffh 1f8000h?1fffffh sa71 1000000xxx 64/32 400000h?40ffffh 200000h?207fffh sa72 1000001xxx 64/32 410000h?41ffffh 208000h?20ffffh sa73 1000010xxx 64/32 420000h?42ffffh 210000h?217fffh sa74 1000011xxx 64/32 430000h?43ffffh 218000h?21ffffh sa75 1000100xxx 64/32 440000h?44ffffh 220000h?227fffh sa76 1000101xxx 64/32 450000h?45ffffh 228000h?22ffffh sa77 1000110xxx 64/32 460000h?46ffffh 230000h?237fffh table 3. s29gl064a bottom boot sector architecture (continued) sector sector address a21?a12 sector size (kbs/kwords) (x8) address range (x16) address range
28 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information sa78 1000111xxx 64/32 470000h?47ffffh 238000h?23ffffh sa79 1001000xxx 64/32 480000h?48ffffh 240000h?247fffh sa80 1001001xxx 64/32 490000h?49ffffh 248000h?24ffffh sa81 1001010xxx 64/32 4a0000h?4affffh 250000h?257fffh sa82 1001011xxx 64/32 4b0000h?4bffffh 258000h?25ffffh sa83 1001100xxx 64/32 4c0000h?4cffffh 260000h?267fffh sa84 1001101xxx 64/32 4d0000h?4dffffh 268000h?26ffffh sa85 1001110xxx 64/32 4e0000h?4effffh 270000h?277fffh sa86 1001111xxx 64/32 4f0000h?4fffffh 278000h?27ffffh sa87 1010000xxx 64/32 500000h?50ffffh 280000h?28ffffh sa88 1010001xxx 64/32 510000h?51ffffh 288000h?28ffffh sa89 1010010xxx 64/32 520000h?52ffffh 290000h?297fffh sa90 1010011xxx 64/32 530000h?53ffffh 298000h?29ffffh sa91 1010100xxx 64/32 540000h?54ffffh 2a0000h?2a7fffh sa92 1010101xxx 64/32 550000h?55ffffh 2a8000h?2affffh sa93 1010110xxx 64/32 560000h?56ffffh 2b0000h?2b7fffh sa94 1010111xxx 64/32 570000h?57ffffh 2b8000h?2bffffh sa95 1011000xxx 64/32 580000h?58ffffh 2c0000h?2c7fffh sa96 1011001xxx 64/32 590000h?59ffffh 2c8000h?2cffffh sa97 1011010xxx 64/32 5a0000h?5affffh 2d0000h?2d7fffh sa98 1011011xxx 64/32 5b0000h?5bffffh 2d8000h?2dffffh sa99 1011100xxx 64/32 5c0000h?5cffffh 2e0000h?2e7fffh sa100 1011101xxx 64/32 5d0000h?5dffffh 2e8000h?2effffh sa101 1011110xxx 64/32 5e0000h?5effffh 2f0000h?2fffffh sa102 1011111xxx 64/32 5f0000h?5fffffh 2f8000h?2fffffh sa103 1100000xxx 64/32 600000h?60ffffh 300000h?307fffh sa104 1100001xxx 64/32 610000h?61ffffh 308000h?30ffffh sa105 1100010xxx 64/32 620000h?62ffffh 310000h?317fffh sa106 1100011xxx 64/32 630000h?63ffffh 318000h?31ffffh sa107 1100100xxx 64/32 640000h?64ffffh 320000h?327fffh sa108 1100101xxx 64/32 650000h?65ffffh 328000h?32ffffh sa109 1100110xxx 64/32 660000h?66ffffh 330000h?337fffh sa110 1100111xxx 64/32 670000h?67ffffh 338000h?33ffffh sa111 1101000xxx 64/32 680000h?68ffffh 340000h?347fffh sa112 1101001xxx 64/32 690000h?69ffffh 348000h?34ffffh sa113 1101010xxx 64/32 6a0000h?6affffh 350000h?357fffh table 3. s29gl064a bottom boot sector architecture (continued) sector sector address a21?a12 sector size (kbs/kwords) (x8) address range (x16) address range
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 29 advance information autoselect mode the autoselect mode provides manufacturer an d device identification, and sector group pro- tection verification, through identifier codes output on dq7?dq0. this mode is primarily intended for programming equipment to automa tically match a device to be programmed with its corresponding programming algorithm. ho wever, the autoselect codes can also be ac- cessed in-system through the command register. when using programming equipment, the autose lect mode requires vid on address pin a9. address pins a6, a3, a2, a1, and a0 must be as shown in ta b l e 4 . in addition, when verifying sector protection, the sector address must a ppear on the appropriate highest order address bits. ta b l e 4 shows the remaining address bits that are don?t care. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq7?dq0. to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in ta b l e 1 0 . this method does not require v id . refer to the autoselect command sequence section for more information. sa114 1101011xxx 64/32 6b0000h?6bffffh 358000h?35ffffh sa115 1101100xxx 64/32 6c0000h?6cffffh 360000h?367fffh sa116 1101101xxx 64/32 6d0000h?6dffffh 368000h?36ffffh sa117 1101110xxx 64/32 6e0000h?6effffh 370000h?377fffh sa118 1101111xxx 64/32 6f0000h?6fffffh 378000h?37ffffh sa119 1110000xxx 64/32 700000h?70ffffh 380000h?387fffh sa120 1110001xxx 64/32 710000h?71ffffh 388000h?38ffffh sa121 1110010xxx 64/32 720000h?72ffffh 390000h?397fffh sa122 1110011xxx 64/32 730000h?73ffffh 398000h?39ffffh sa123 1110100xxx 64/32 740000h?74ffffh 3a0000h?3a7fffh sa124 1110101xxx 64/32 750000h?75ffffh 3a8000h?3affffh sa125 1110110xxx 64/32 760000h?76ffffh 3b0000h?3b7fffh sa126 1110111xxx 64/32 770000h?77ffffh 3b8000h?3bffffh sa127 1111000xxx 64/32 780000h?78ffffh 3c0000h?3c7fffh sa128 1111001xxx 64/32 790000h?79ffffh 3c8000h?3cffffh sa129 1111010xxx 64/32 7a0000h?7affffh 3d0000h?3d7fffh sa130 1111011xxx 64/32 7b0000h?7bffffh 3d8000h?3dffffh sa131 1111100xxx 64/32 7c0000h?7cffffh 3e0000h?3e7fffh sa132 1111101xxx 64/32 7d0000h?7dffffh 3e8000h?3effffh sa133 1111110xxx 64/32 7e0000h?7effffh 3f0000h?3f7fffh sa134 1111111000 64/32 7f0000h?7fffffh 3f8000h?3fffffh table 3. s29gl064a bottom boot sector architecture (continued) sector sector address a21?a12 sector size (kbs/kwords) (x8) address range (x16) address range
30 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information ta b l e 4 . autoselect codes, (high voltage method) legend: l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care. sector group protection and unprotection the hardware sector group protection feature di sables both program and erase operations in any sector group. in this device, a sector group consists of four adjacent sectors that are pro- tected or unprotected at the same time (see ta b l e 4 ). the hardware sector group unprotection feature re-enables both program an d erase operations in previously protected sector groups. sector group protection/unpro tection can be implemented via two methods. sector protection/unprotection requires v id on the reset# pin only, and can be implemented either in-system or via programming equipment. figure 2 shows the algorithms and figure 23 shows the timing diagram. this method us es standard microprocessor bus cycle timing. for sector group unprotect, all unprotected sector groups must first be protected prior to the first sector group unprotect write cycle. the device is shipped with all sector groups unprotected. spansion offe rs the option of pro- gramming and protecting sector groups at its factory prior to shipping the device through spansion programming service. contact a spansion represen tative for details. it is possible to determine whether a sector group is protected or unprotected. see the au- toselect mode section for details. description ce# oe# we # a22 to a15 a14 to a10 a9 a8 to a7 a6 a5 to a4 a3 to a2 a1 a0 dq8 to dq15 dq7 to dq0 byte# = v ih byte# = v il manufacturer id : spansion products llhxxv id x l x l l l 00 x 01h s29gl064a cycle 1 llhxxv id xlx llh 22 x 7eh cycle 2 h h l 22 x 10h cycle 3 hhh 22 x 00h (bottom boot) 01h (top boot) sector group protection verification llhsaxv id xlxlhl x x 01h (protected), 00h (unprotected) secured silicon sector indicator bit (dq7), wp# protects highest address sector llhxxv id xlxlhh x x 98h (factory locked), 18h (not factory locked) secured silicon sector indicator bit (dq7), wp# protects lowest address sector llhxxv id xlxlhh x x 88h (factory locked), 08h (not factory locked)
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 31 advance information ta b l e 5 . s29gl064a sector group protection/unprotection address top boot sector bottom boot sector sector group a21?a15 sa0 0000000 sa1 0000001 sa2 0000010 sa3 0000011 sa4?sa7 00001xx sa8?sa11 00010xx sa12?sa15 00011xx sa16?sa19 00100xx sa20?sa23 00101xx sa24?sa27 00110xx sa28?sa31 00111xx sa32?sa35 01000xx sa36?sa39 01001xx sa40?sa43 01010xx sa44?sa47 01011xx sa48?sa51 01100xx sa52?sa55 01101xx sa56?sa59 01110xx sa60?sa63 01111xx sa64?sa67 10000xx sa68?sa71 10001xx sa72?sa75 10010xx sa76?sa79 10011xx sa80?sa83 10100xx sa84?sa87 10101xx sa88?sa91 10110xx sa92?sa95 10111xx sa96?sa99 11000xx sa100?sa103 11001xx sa104?sa107 11010xx sa108?sa111 11011xx sa112?sa115 11100xx sa116?sa119 11101xx sa120?sa123 11110xx sa124 1111100 sa125 1111101 sa126 1111110 sa127 1111111
32 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information temporary sector group unprotect this feature allows temporary unprotection of previously protected sector groups to change data in-system. the sector group unprotect mode is activated by setting the reset# pin to v id . during this mode, formerly protected sect or groups can be programmed or erased by selecting the sector group addresses. once v id is removed from the reset# pin, all the pre- viously protected sector groups are protected again. figure 1 shows the algorithm, and figure 23 shows the timing diagrams, for this feature. notes: 1. all protected sector groups unprotected (if wp# = v il , the first or last sector will remain protected). 2. all previously protected sector groups are protected once again. figure 1. temporary sector group unprotect operation start perform erase or program operations reset# = v ih te m p o ra r y s e c t o r group unprotect completed (note 2) reset# = v id (note 1)
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 33 advance information figure 2. in-system sector group protect/unprotect algorithms sector group protect: write 60h to sector group address with a6?a0 = 0xx0010 set up sector group address wait 150 s verify sector group protect: write 40h to sector group address with a6?a0 = 0xx0010 read from sector group address with a6?a0 = 0xx0010 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector group protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector group unprotect mode no sector group unprotect: write 60h to sector group address with a6?a0 = 1xx0010 set up first sector group address wait 15 ms verify sector group unprotect: write 40h to sector group address with a6?a0 = 1xx0010 read from sector group address with a6?a0 = 1xx0010 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector group verified? remove v id from reset# write reset command sector group unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector group unprotect mode no all sector groups protected? yes protect all sector groups: the indicated portion of the sector group protect algorithm must be performed for all unprotected sector groups prior to issuing the first sector group unprotect address set up next sector group address no yes no yes no no yes no sector group protect algorithm sector group unprotect algorithm first write cycle = 60h? protect another sector group? reset plscnt = 1
34 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information secured silicon sector flash memory region the secured silicon sector feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn). the secured silicon sector is 256 bytes in length, and uses a secured silicon sector indicator bit (dq7 ) to indicate whether or not the secured silicon sector is locked when shipped from the factory. this bit is perma- nently set at the factory and cannot be changed, which prevents cloning of a factory locked part. this ensures the security of the esn once the product is shipped to the field. the factory offers the device with the secured silicon sector either customer lockable (stan- dard shipping option) or factory locked (contact a spansion sales representative for ordering information). the customer-lockable version is shipped with the secured silicon sector un- protected, allowing customers to program the sector after receiving the device. the customer-lockable version also has the secured silicon sector indicator bit permanently set to a ?0.? the factory-locked version is always protected when shipped from the factory, and has the secured silicon sector indicator bit pe rmanently set to a ?1.? thus, the secured sil- icon sector indicator bit prevents customer-l ockable devices from being used to replace devices that are factory locked. note that the acc function an d unlock bypass modes are not available when the secured silicon sector is enabled. the secured silicon sector address space in this device is allocated as follows: the system accesses the secured silicon sector through a command sequence (see ?write protect (wp#)?). after the system has written the enter secured silicon sector command se- quence, it may read the secured silicon sector by using the addresses normally occupied by the first sector (sa0). this mode of operation continues until the system issues the exit se- cured silicon sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to sector sa0. customer lockable: secured sili con sector not programmed or protected at the factory unless otherwise specified, the device is ship ped such that the customer may program and protect the 256-byte secured silicon sector. the system may program the secured silicon se ctor using the write-buffer, accelerated and/ or unlock bypass methods, in addition to th e standard programming command sequence. see command definitions . programming and protecting the secured silicon se ctor must be used with caution since, once protected, there is no procedure available for unprotecting the secured silicon sector area and none of the bits in the secured silicon se ctor memory space can be modified in any way. the secured silicon sector area can be prot ected using one of the following procedures: ? write the three-cycle enter secured silicon sector region command sequence, and then follow the in-system sector pr otect algorithm as shown in figure 2 , except that reset# may be at either v ih or v id . this allows in-system protection of the secured silicon sector without raising any device pin to a high voltage. note that this method is only applicable to the secured silicon sector. ? to verify the protect/unprotect status of th e secured silicon sector, follow the algorithm shown in figure 1 . secured silicon sector address range customer lockable esn factory locked expressflash factory locked 000000h?000007h determined by customer esn esn or determined by customer 000008h?00007fh unavailable determined by customer
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 35 advance information once the secured silicon sector is programmed, locked and verified, the system must write the exit secured silicon sector region command sequence to return to reading and writing within the remainder of the array. factory locked: secured silicon se ctor programmed and protected at the factory in devices with an esn, the secured silicon se ctor is protected when the device is shipped from the factory. the secured silicon sector ca nnot be modified in any way. an esn factory locked device has an 16-byte random esn at addresses 000000h?000007h. please contact your sales representative for details on ordering esn factory locked devices. customers may opt to have their code programm ed by the factory through the spansion pro- gramming service (customer factory locked). th e devices are then shipped from the factory with the secured silicon sector permanently lock ed. contact your sales representative for de- tails on using the spansion programming service. write protect (wp#) the write protect function provides a hardware me thod of protecting the first or last sector group without using v id . write protect is one of two functions provided by the wp#/acc input. if the system asserts v il on the wp#/acc pin, the device disables program and erase func- tions in the first or last sector group inde pendently of whether those sector groups were protected or unprotected. note that if wp#/acc is at v il when the device is in the standby mode, the maximum input load current is increased. see the table in ?dc characteristics? sec- tion on page 60 . if the system asserts v ih on the wp#/acc pin, the devi ce reverts to whether the first or last sector was previously set to be protected or unprotected using the method described in ?sector grou p protection and unprotection?. note that wp# has an internal pullup; when unconnected, wp# is at v ih . hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvert ent writes (refer to tables 16 and 17 for command defini- tions). in addition, the following hardware data protection measures prevent accidental erasure or programming, which mi ght otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command re gister and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 3 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to ini- tiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one.
36 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up. common flash memory interface (cfi) the common flash interface (cfi) specification outlines device and host system software in- terrogation handshake, which allows specific vend or-specified software algorithms to be used for entire families of devices. software supp ort can then be device-independent, jedec id- independent, and forward- and backward-compati ble for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h, any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 27 -30. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 27-30. the system must writ e the reset command to return the device to reading array data. for further information, please refer to the cfi specification and cfi publication 100, avail- able via the world wide web at http://www.amd. com/flash/cfi. alternat ively, contact your sales representative for copies of these documents.
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 37 advance information ta b l e 6 . cfi query identification string table 7. system interface string note: cfi data related to v cc and time-outs may differ from actual vcc and time -outs of the product. please consult the ordering information tables to obtain the v cc range for particular part numbers. please contact the erase and programming performance table for typical timeout specifications. addresses (x16) addresses (x8) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extend ed table (00h = none exists) addresses (x16) addresses (x8) data description 1bh 36h 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 38h 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 3ah 0000h v pp min. voltage (00h = no v pp pin present) 1eh 3ch 0000h v pp max. voltage (00h = no v pp pin present) 1fh 3eh 0007h reserved for future use 20h 40h 0007h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 42h 000ah typical timeout per individual block erase 2 n ms 22h 44h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 46h 0001h reserved for future use 24h 48h 0005h max. timeout for buffer write 2 n times typical 25h 4ah 0004h max. timeout per individual block erase 2 n times typical 26h 4ch 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
38 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information ta b l e 8 . device geometry definition ta b l e 9 . primary vendor-specific extended query addresses (x16) addresses (x8) data description 27h 4eh 00xxh device size = 2 n byte 0017h = 64 mb 28h 29h 50h 52h 000xh 0000h flash device interface descriptio n (refer to cfi publication 100) 0000h = x8-only bus devices 0001h = x16-only bus devices 0002h = x8/x16 bus devices 2ah 2bh 54h 56h 0005h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 58h 00xxh number of erase block regions within device (01h = uniform device, 02h = boot device) 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 00xxh 000xh 00x0h 000xh erase block region 1 information (refer to the cfi specification or cfi publication 100) 007fh, 0000h, 0000h, 0001h = 64 mb 31h 32h 33h 34h 60h 64h 66h 68h 00xxh 0000h 0000h 000xh erase block region 2 information (refer to cfi publication 100) 0000h, 0000h, 0000h, 0000h =64 mb 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0000h erase block region 3 information (refer to cfi publication 100) 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h erase block region 4 information (refer to cfi publication 100) addresses (x16) addresses (x8) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 86h 0031h major version number, ascii 44h 88h 0033h minor version number, ascii 45h 8ah 000xh address sensitive unlock (bits 1-0) 0 = required, 1 = not required process technology (bits 7-2) 0010b = 200 nm mirrorbit 0009h = x8-only bus devices 0008h = all other devices 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 90h 0000h sector temporary unprotect 00 = not supported, 01 = supported
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 39 advance information 49h 92h 0004h sector protect/unprotect scheme 0004h = standard mode (refer to text) 4ah 94h 0000h simultaneous operation 00 = not supported, x = number of sectors in bank 4bh 96h 0000h burst mode type 00 = not supported, 01 = supported 4ch 98h 0001h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 9ah 00b5h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 9ch 00c5h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 9eh 00xxh top/bottom boot sector flag 00h = uniform device without wp # protect, 02h = bottom boot device, 03h = top boot device, 04h = uniform sectors bottom wp# protect, 05h = uniform sectors top wp# protect 50h a0h 0001h program suspend 00h = not supported, 01h = supported addresses (x16) addresses (x8) data description
40 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information command definitions writing specific address and data commands or se quences into the comman d register initiates device operations. ta b l e 1 0 defines the valid register command sequences. writing incorrect address and data values or writ ing them in the improper sequ ence may place the device in an unknown state. a reset command is then required to return the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the ac char- acteristics section for timing diagrams. reading array data the device is automatically set to reading ar ray data after device power-up. no commands are required to retrieve data. the device is ready to read array data after completing an em- bedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase-suspend- read mode, after which the system can read da ta from any non-erase-suspended sector. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see the erase suspend/erase resume commands section for more information. the system must issue the reset command to return th e device to the read (or erase-sus- pend-read) mode if dq5 goes high during an active program or erase operation, or if the device is in the autoselect mode. see the next section, reset command, for more information. see also requirements for reading array data in the device bus operations section for more information. the read-only operations? ?ac characteristics? section on page 63 provides the read parameters, and figure 13 shows the timing diagram. reset command writing the reset command resets the device to the read or erase-suspend-read mode. ad- dress bits are don?t cares for this command. the reset command may be written between the sequence cycles in an erase command se- quence before erasing begins. this resets the device to the read mode. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command se- quence before programming begins. this resets the device to the read mode. if the program command sequence is written while the device is in the erase suspend mode, writing the reset command returns the device to the eras e-suspend-read mode. once programming be- gins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the rese t command must be written to return to the read mode. if the device entered the autoselect mode while in the erase suspend mode, writ- ing the reset command returns the devi ce to the erase-suspend-read mode. if dq5 goes high during a program or erase op eration, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in erase suspend). note that if dq1 goes high during a write buffer programming operation, the system must write the write-to-buffer-abort reset command sequence to reset the device for the next operation.
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 41 advance information autoselect command sequence the autoselect command sequence allows the host system to read several identifier codes at specific addresses: note: the device id is read over th ree cycles. sa = sector address the autoselect command sequence is initiated by first writing two unlock cycles. this is fol- lowed by a third write cycle that contains the autoselect command. the device then enters the autoselect mode. the system may read at any address any number of times without ini- tiating another autoselect command sequence: the system must write the reset command to return to the read mode (or erase-suspend- read mode if the device was previously in erase suspend). enter secured silicon sect or/exit secured silicon sector command sequence the secured silicon sector region provides a se cured data area containing an 8-word/16-byte random electronic serial number (esn). the system can access the secured silicon sector region by issuing the three-cycle enter secu red silicon sector command sequence. the de- vice continues to access the secured silicon sect or region until the system issues the four- cycle exit secured silicon sector command se quence. the exit secured silicon sector com- mand sequence returns the device to normal operation. ta b l e 1 0 shows the address and data requirements for both command sequences. see also ?secured silicon sector flash memory region? for further information. note that the acc function and unlock bypass modes are not available when the secured silicon sector is enabled. word program command sequence programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program ad- dress and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further cont rols or timings. the device automatically pro- vides internally generated program pulses and verifies the programmed cell margin. tables 31 and 32 show the address and data requir ements for the word program command se- quence, respectively. when the embedded program algorithm is comple te, the device then returns to the read mode and addresses are no longer latched. th e system can determine the status of the pro- gram operation by using dq7 or dq6. refer to the write operation status section for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that the secured silicon sector, autoselect, and cfi functions are unavailable when a pr ogram operation is in progress. note that a hardware reset immediately terminates the program op eration. the program command sequence should be reinitiated once the device has return ed to the read mode, to ensure data integrity. identifier code a7:a0 (x16) a6:a-1 (x8) manufacturer id 00h 00h device id, cycle 1 01h 02h device id, cycle 2 0eh 1ch device id, cycle 3 0fh 1eh secured silicon sector factory protect 03h 06h sector protect verify (sa)02h (sa)04h
42 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information programming is allowed in any sequence of a ddress locations and across sector boundaries. programming to the same word address multiple times without intervening erases (incremen- tal bit programming) requires a modified programming method. for such application requirements, please contact your local spansi on representative. word programming is sup- ported for backward compatibility with existing flash driver software and for occasional writing of individual words. use of write buffer programming (see below) is strongly recom- mended for general programming use when more than a few words are to be programmed. the effective word programming time using wr ite buffer programming is approximately four times shorter than the single word programming time. any bit in a word cannot be programmed from ?0? back to a ?1.? attempting to do so may cause the device to set dq5=1, or cause dq 7 and dq6 status bits to indicate the oper- ation was successful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the system to program words to the device faster than using the standard program command se quence. the unlock bypass co mmand sequence is initiated by first writing two unlock cycles. this is follow ed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass mode command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock by pass program command, a0h; the second cycle contains the program address and data. addition al data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program com- mand sequence, resulting in faster total programming time. tables 31 and 32 show the requirements for the command sequence. during the unlock bypass mode, only the unlo ck bypass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. the first cycle must contain the data 90h. the sec- ond cycle must contain the data 00h. the device then returns to the read mode. write buffer programming write buffer programming allows the system writ e to a maximum of 16 words/32 bytes in one programming operation. this results in faster effective programming ti me than the standard programming algorithms. the write buffer programming command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer load command written at the sector a ddress in which programming will occur. the fourth cycle writes the sector address and the number of word location s, minus one, to be programmed. for example, if the system will program 6 unique address locations, then 05h should be written to the device. this tells the device how many write buffer addresses will be loaded with data and therefore when to ex pect the program buffer to flash command. the number of locations to program cannot exceed th e size of the write buffer or the operation will abort. the fifth cycle writes the first address location and data to be programmed. the write-buffer- page is selected by address bits a max ?a 4 . all subsequent address/data pairs must fall within the selected-write-buffer-page. the system then writes the remaining a ddress/data pairs into the write buffer. write buffer locations may be loaded in any order. the write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (this means write buffer progra mming cannot be performed across multiple write-buffer pages.) this also means that write buffer programming cannot be performed across multiple sectors. if the system attempts to load programming da ta outside of the se- lected write-buffer page, the operation will abort.
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 43 advance information note that if a write buffer address location is loaded multiple times, the address/data pair counter will be decremented for every data load operation. the host system must therefore account for loading a wr ite-buffer location more than once . the counter decrements for each data load operation, not for ea ch unique write-buffer-address loca tion. note also that if an address location is loaded more than once into the buffer, the final data loaded for that ad- dress will be programmed. once the specified number of write buffer locati ons have been loaded, the system must then write the program buffer to flash command at th e sector address. any other address and data combination aborts the write buffer programming operation. the device then begins pro- gramming. data polling should be used while moni toring the last address location loaded into the write buffer. dq7, dq6, dq5, and dq1 should be monitored to determine the device sta- tus during write buffer programming. the write-buffer programming operation can be suspended using the standard program sus- pend/resume commands. upon successful completion of the write buffer programming operation, the device is ready to execute the next command.
44 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information the write buffer programming sequence ca n be aborted in the following ways: ? load a value that is greater than the page bu ffer size during the number of locations to program step. ? write to an address in a sector different than the one specified during the write-buffer- load command. ? write an address/data pair to a different write-buffer-page than the one selected by the starting address during the write buffer data loading stage of the operation. ? write data other than the confirm command af ter the specified number of data load cy- cles. the abort condition is indicated by dq1 = 1, dq7 = data# (for the last address location loaded), dq6 = toggle, and dq5=0. a write-to -buffer-abort reset command sequence must be written to reset the devi ce for the next operation. note that the secured silicon sector, autosele ct, and cfi functions are unavailable when a program operation is in progress. this flash device is capable of handling multiple write buffer programming operations on the same write buffer address range without intervening erases. for applications requiring incremental bit prog ramming, a modified programming method is required; please contact your local spansion representative. any bit in a write buffer ad- dress range cannot be programmed from ?0? back to a ?1.? attempting to do so may cause the device to set dq5=1, of cause the dq7 and dq6 status bits to indicate the opera- tion was successful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? accelerated program the device offers accelerated program operations through the wp#/acc or acc pin depend- ing on the particular product. when the system asserts v hh on the wp#/acc or acc pin. the device uses the higher voltage on the wp#/ac c or acc pin to accele rate the operation. note that the wp#/ acc pin must not be at v hh for operations other th an accelerated program- ming, or device damage may result. wp# has an internal pullup; when unconnected, wp# is at v ih . figure 4 illustrates the algorithm for the program operation. refer to the erase and program operations? ?ac characteristics? section on page 63 section for parameters, and figure 16 for timing diagrams.
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 45 advance information figure 3. write buffer programming operation write ?write to buffer? command and sector address write number of addresses to program minus 1(wc) and sector address write program buffer to flash sector address write first address/data write to a different sector address fail or abort pass read dq7 - dq0 at last loaded address read dq7 - dq0 with address = last loaded address write next address/data pair wc = wc - 1 wc = 0 ? part of ?write to buffer? command sequence ye s ye s ye s ye s ye s ye s no no no no no no abort write to buffer operation? dq7 = data? dq7 = data? dq5 = 1? dq1 = 1? write to buffer aborted. must write ?write-to-buffer abort reset? command sequence to return to read mode. (note 2) (note 3) (note 1) notes: 1. when sector address is specified, any address in the selected sector is acceptable. however, when loading write-buffer address locations with data, all addresses must fall within the selected write-buffer page. 2. dq7 may change simultaneously with dq5. therefore, dq7 should be verified. 3. if this flowchart location was reached because dq5= ?1?, then the device failed. if this flowchart location was reached because dq1= ?1?, then the write to buffer operation was aborted. in either case, the proper reset command must be written before the device can begin another operation. if dq1=1, write the write-buffer-programming-abort- reset command. if dq5=1, write the reset command. 4. see table 10 and for command sequences required for write buffer programming.
46 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information note: see table 10 for program command sequence . figure 4. program operation program suspend/program resume command sequence the program suspend command allows the system to interrupt a programming operation or a write to buffer programming operation so that data can be read fr om any non-suspended sector. when the program suspend command is written during a programming process, the device halts the program operation within 15 s maximum (5s typica l) and updates the sta- tus bits. addresses are not required wh en writing the program suspend command. after the programming operation has been suspended, the system can read array data from any non-suspended sector. the program suspend command may also be issued during a pro- gramming operation while an erase is suspended . in this case, data may be read from any addresses not in erase suspend or program suspend. if a read is needed from the secured silicon sector area (one-time program area), then user must use the proper command se- quences to enter and exit this region. note th at the secured silicon sector, autoselect, and cfi functions are unavailable when a program operation is in progress. the system may also write the autoselect command sequence wh en the device is in the pro- gram suspend mode. the system can read as ma ny autoselect codes as required. when the device exits the autoselect mo de, the device reverts to the program suspend mode, and is ready for another valid operation. see autosele ct command sequence for more information. after the program resume command is written, the device reverts to programming. the sys- tem can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see wr ite operation status for more information. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 47 advance information the system must write the program resume co mmand (address bits are don?t care) to exit the program suspend mode and continue the pr ogramming operation. further writes of the resume command are ignored. another progra m suspend command can be written after the device has resumed programming.
48 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information figure 5. program suspend/program resume chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writ- ing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, whic h in turn invokes the embedded erase algo- rithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatica lly preprograms and verifies the enti re memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. ta b l e 1 0 shows the address and data re quirements for the chip erase command sequence. when the embedded erase algorithm is complete , the device returns to the read mode and addresses are no longer latched. the system ca n determine the status of the erase operation by using dq7, dq6, or dq2. refer to the write operation status section for information on these status bits. any commands written during the chip erase op eration are ignored. however, note that a hardware reset immediately terminates the erase operat ion. if that occurs, the chip erase command sequence should be reinitiated once th e device has returned to reading array data, to ensure data integrity. figure 6 illustrates the algorithm for the erase oper ation. refer to the erase and program op- erations table in the ac characte ristics section for parameters, and figure 18 section for timing diagrams. program operation or write-to-buffer sequence in progress write program suspend command sequence command is also valid for erase-suspended-program operations autoselect and secsi sector read operations are also allowed data cannot be read from erase- o r program-suspended sectors write program resume command sequence read data as required done reading? no yes write address/data xxxh/30h device reverts to operation prior to program suspend write address/data xxxh/b0h wait 15 s
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 49 advance information sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set- up command. two addition al unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. ta b l e 1 0 shows the address and data requirem ents for the sector erase command sequence. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically programs and verifies th e entire memory for an all zero data pattern prior to electrical erase. the system is not requ ired to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time betw een these additional cycles must be less than 50 s, otherwise erasure may begin. any sect or erase address and command following the exceeded time-out may or may not be accepted . it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sect or erase command is written. any command other than sec- tor erase or erase suspend duri ng the time-out period rese ts the device to the read mode. note that the secured silicon sector, auto select, and cfi functions are unavailable when an erase operation is in progress . the system must rewrite the command sequence and any additional addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out (see the section on dq3: sector erase timer.). the time-o ut begins from the rising edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete , the device returns to reading array data and addresses are no longer latched. the syst em can determine the status of the erase op- eration by reading dq7, dq6, or dq2 in the erasing sector. refer to the write operation status section for informat ion on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once the device has returned to readin g array data, to ensure data integrity.
50 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information figure 6 illustrates the algorithm for the erase oper ation. refer to the erase and program op- erations table in the ac characte ristics section for parameters, and figure 18 section for timing diagrams. notes: 1. see table 10 for program command sequence. 2. see the section on dq3 for information on the sector erase timer. figure 6. erase operation erase suspend/erase resume commands the erase suspend command, b0h, allows the sy stem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this com- mand is valid only during the sector erase op eration, including the 50 s time-out period during the sector erase command sequence. th e erase suspend command is ignored if writ- ten during the chip erase operatio n or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a typical of 5 s ( maximum of 20 s) to suspend the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device immedi- ately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the device enters the erase-suspend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) reading at any address within erase-suspended sectors produces status information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-sus- pended. refer to the write operation status se ction for information on these status bits. after an erase-suspended program operation is complete, the device returns to the erase- suspend-read mode. the system can determine th e status of the program operation using the dq7 or dq6 status bits, just as in the standa rd word program operation. refer to the write operation status section for more information. in the erase-suspend-read mode, the system can also issue the autoselect command se- quence. refer to the ?autoselect mode? section on page 29 and ?autoselect command sequence? section on page 41 sections for details. to resume the sector erase operation, the sy stem must write the er ase resume command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing. start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 51 advance information note: during an erase operation, this flas h device performs multiple internal oper- ations which are invisible to the system. wh en an erase operation is suspended, any of the internal operations that were not fu lly completed must be restarted. as such, if this flash device is continually issu ed suspend/resume commands in rapid suc- cession, erase progress will be impeded as a function of the number of suspends. the result will be a longer cumulative er ase time than without suspends. note that the additional suspends do not affect devi ce reliability or future performance. in most systems rapid erase/suspend activity oc curs only briefly. in such cases, erase performance will not be significantly impacted.
52 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information command definitions ta b l e 1 0 . command definitions (x16 mode, byte# = v ih ) command sequence (note 1) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset (note 7) 1 xxx f0 autoselect (note 8) manufacturer id 4 555 aa 2aa 55 555 90 x00 0001 device id (note 9) 4 555 aa 2aa 55 555 90 x01 227e x0e (note 18) x0f (note 18) secured silicon sector factory protect (note 10) 4 555 aa 2aa 55 555 90 x03 (note 10) sector group protect verify (note 12) 4 555 aa 2aa 55 555 90 (sa)x02 00/01 enter secured silicon sector region 3 555 aa 2aa 55 555 88 exit secured silicon sector region 4 555 aa 2aa 55 555 90 xxx 00 program 4 555 aa 2aa 55 555 a0 pa pd write to buffer (note 11) 3 555 aa 2aa 55 sa 25 sa wc pa pd wbl pd program buffer to flash 1 sa 29 write to buffer abort reset (note 13) 3 555 aa 2aa 55 555 f0 unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program (note 14) 2 xxx a0 pa pd unlock bypass reset (note 15) 2 xxx 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 program/erase suspend (note 16) 1 xxx b0 program/erase resume (note 17) 1 xxx 30 cfi query (note 18) 1 55 98 legend: x = don?t care ra = read address of memory location to be read. rd = read data read from location ra during read operation. pa = program address. addresses latch on falling edge of we# or ce# pulse, whichever happens later. pd = program data for location pa. data latches on rising edge of we# or ce# pulse, whichever happens first. sa = sector address of sector to be verified (in autoselect mode) or erased. address bits a21?a15 uniquely select any sector. wbl = write buffer location. address must be within same write buffer page as pa. wc = word count. number of write buffer locations to load minus 1. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells indicate read cycles. all others are write cycles. 4. during unlock and command cycles , when lower address bits are 555 or 2aa as shown in table, address bits above a11 and data bits above dq7 are don?t care. 5. no unlock or command cycles required when device is in read mode. 6. reset command is required to re turn to read mode (or to erase- suspend-read mode if previously in erase suspend) when device is in autoselect mode, or if dq5 goes high while device is providing status information. 7. fourth cycle of the autoselect command sequence is a read cycle. data bits dq15?dq8 are don?t care. except for rd, pd and wc. see autoselect command sequence section for more information. 8. device id must be read in three cycles. 9. if wp# protects highest address sector, data is 98h for factory locked and 18h for not factory lo cked. if wp# protects lowest address sector, data is 88h for factory locked and 08h for not factor locked. 10. data is 00h for an unprotected sector group and 01h for a protected sector group. 11. total number of cycles in co mmand sequence is determined by number of words written to write buffer. maximum number of cycles in command sequence is 21, including ?program buffer to flash? command. 12. command sequence resets device for next command after aborted write-to-buffer operation. 13. unlock bypass command is requ ired prior to unlock bypass program command. 14. unlock bypass reset command is required to return to read mode when device is in unlock bypass mode. 15. system may read and program in non-erasing sectors, or enter autoselect mode, when in erase suspend mode. erase suspend command is valid only during a sector erase operation. 16. erase resume command is valid only during erase suspend mode. 17. command is valid when device is ready to read array data or when device is in autoselect mode. 18. refer to table 4, autoselect codes for individual device ids per device density and model number.
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 53 advance information write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. ta b l e 1 1 and the following subsections describe the function of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. the device also provides a hardware-based output sig- nal, ry/by#, to determine whether an embedded program or erase operation is in progress or has been completed. dq7: data# polling the data# polling bit, dq7, in dicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the de vice outputs on dq7 the complement of the datum programmed to dq7. this dq7 status al so applies to programming during erase sus- pend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status in- formation on dq7. if a program address falls wi thin a protected sector, data# polling on dq7 is active for approximately 1 s, then the device returns to the read mode. during the embedded erase algo rithm, data# polling produces a ?0? on dq7. when the em- bedded erase algorithm is complete, or if the device enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximatel y 100 s, then the device returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the un- protected sectors, and ignores the selected sector s that are protected. however, if the system reads dq7 at an address within a protec ted sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq0? dq6 may be still invalid. valid data on dq0?dq7 will appear on successive read cycles. ta b l e 1 1 shows the outputs for data# polling on dq7. figure 7 shows the data# polling al- gorithm. figure 19 in the ac characteristics section sh ows the data# polling timing diagram.
54 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5. figure 7. data# polling algorithm ry/by#: ready/busy# the ry/by# is a dedicated, open-drain output pin which indicates whether an embedded al- gorithm is in progress or complete. the ry/by# st atus is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, several ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively erasing or programming. (this includes pro- gramming in the erase suspend mode.) if the output is high (ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. ta b l e 1 1 shows the outputs for ry/by#. dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq15?dq0 addr = va read dq15?dq0 addr = va dq7 = data? start
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 55 advance information dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the com- mand sequence (prior to the program or erase operation), and during the sector erase time- out. during an embedded program or erase algorithm operation, successive read cycles to any ad- dress cause dq6 to toggle. the system may use ei ther oe# or ce# to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 100 s, then return s to reading array data . if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ig- nores the selected sectors that are protected. the system can use dq6 and dq2 together to de termine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase al- gorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops toggling. however, the sy stem must also use dq2 to determine which sectors are eras- ing or erase-suspended. alternatively, the sy stem can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-pr ogram mode, and stops toggling once the em- bedded program algorithm is complete. ta b l e 1 1 shows the outputs for toggle bit i on dq6. figure 8 shows the toggle bit algorithm. figure 20 in the ?ac characteristics? section shows the toggle bit timing diagrams. figure 21 shows the differences between dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii.
56 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information figure 8. toggle bit algorithm start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?dq0 toggle bit = toggle? read dq7?dq0 twice read dq7?dq0 note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information.
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 57 advance information dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a part icular sector is ac- tively erasing (that is, the embedded erase algori thm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresse s within those sectors that have been se- lected for erasure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is active ly erasing, or is in erase suspend, but can- not distinguish which sectors are selected for eras ure. thus, both status bits are required for sector and mode information. refer to ta b l e 1 1 to compare outputs for dq2 and dq6. figure 8 shows the toggle bit algorithm in flowchar t form, and the section ?dq2: toggle bit ii? explains the algorithm. see also the ry/by#: ready/ busy# subsection. figure 20 shows the toggle bit timing diagram. figure 21 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 8 for the following discussion. whenever the system initially begins reading toggle bit status, it must read dq7?dq0 at leas t twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bi t is not toggling, the device ha s completed the program or erase operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether th e toggle bit is toggling, since the toggle bit may have stopped to ggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed th e program or erase operation. if it is still toggling, the device did not completed the oper ation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initia lly determines that th e toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining th e status as described in the previous para- graph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm wh en it returns to determine the status of the operation (top of figure 6 ). dq5: exceeded timing limits dq5 indicates whether the program, erase, or write-to-buffer time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? in dicating that the pro- gram or erase cycle was not successfully completed. the device may output a ?1? on dq5 if the syst em tries to program a ?1? to a location that was previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the devi ce halts the operation, and wh en the timing limit has been exceeded, dq5 produces a ?1.? in all these cases, the system must write the re set command to return the device to the read- ing the array (or to erase-suspend-read if the device was previously in the erase-suspend- program mode).
58 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information dq3: sector erase timer after writing a sector erase command sequen ce, the system may read dq3 to determine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when th e time-out period is complete, dq3 switches from a ?0? to a ?1.? if the time between addi tional sector erase commands from the system can be assumed to be less than 50 s, the syst em need not monitor dq3. see also the sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedd ed erase algorithm has begun; all further com- mands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept additional sect or erase commands. to ensure the command has been accepted, the system software should ch eck the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. ta b l e 1 1 shows the status of dq3 relative to the other status bits. dq1: write-to-buffer abort dq1 indicates whether a write-to-buffer operation was aborted. under these conditions dq1 produces a ?1?. the system must issue the write-to-buffer-abort-reset command sequence to return the device to reading array data . see write buffer section for more details. ta b l e 1 1 . write operation status notes: 1. dq5 switches to ?1? when an embedded pr ogram, embedded erase, or write-to-buffer operation has exceeded the maximum timing li mits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status inform ation. refer to the appropriate subsection for further details. 3. the data# polling algorithm should be used to moni tor the last loaded write-buffer address location. 4. dq1 switches to ?1? when the device has aborted the write-to-buffer operation. status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 ry/ by# standard mode embedded program algorithm dq7# to g g l e 0 n/a no toggle 0 0 embedded erase algorithm 0 to g g l e 0 1 to g g l e n/a 0 program suspend mode program- suspend read program-suspended sector invalid (not allowed) 1 non-program suspended sector data 1 erase suspend mode erase- suspend read erase-suspended sector 1 no toggle 0 n/a to g g l e n/a 1 non-erase suspended sector data 1 erase-suspend-program (embedded program) dq7# to g g l e 0 n/a n/a n/a 0 write-to- buffer busy (note 3) dq7# to g g l e 0 n/a n/a 0 0 abort (note 4) dq7# to g g l e 0 n/a n/a 1 0
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 59 advance information absolute maximum ratings storage temperature, plastic packages . . . . . . . . . . . . . . . . ?65c to +150c ambient temperature with power applied . . . . . . . . . . . . . . ?65c to +125c voltage with respect to ground: v cc (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +4.0 v . . . . . . . . . . . . a9, oe#, acc and reset# (note 2) ?0.5 v to +12.5 v all other pins (note 1) . . . . . . . . . . . . . . . . . . . . . ?0.5 v to v cc +0.5 v output short circuit current (note 3) . . . . . . . . . . . . . . . . . . . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/os is ?0.5 v. during voltage transitions, inputs or i/os may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 9 . maximum dc voltage on input or i/os is v cc + 0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 10 . 2. minimum dc input voltage on pins a9, oe #, acc, and reset# is ?0.5 v. during voltage transitions, a9, oe#, a cc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 9 . maximum dc input voltage on pin a9, oe#, acc, and reset# is +12.5 v which may overshoot to +14.0v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be gr eater than one second. 4. stresses above those listed under ?a bsolute maximum ra tings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions fo r extended periods may affect device reliability. operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . ?40c to +85c supply voltages v cc for full voltage range . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 v to +3.6 v v cc for regulated voltage range . . . . . . . . . . . . . . . . . . . . . +3.0 v to +3.6 v v io . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v cc note: operating ranges define those limits between which the functionality of the device is guaranteed . figure 9. maximum negative overshoot waveform figure 10. maximum positive overshoot waveform 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
60 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information dc characteristics cmos compatible notes: 1. on the wp#/acc pin only, the maximum input load current when wp# = v il is 2.0 a. 2. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 3. maximum i cc specifications are tested with v cc = v cc max. 4. i cc active while embedded erase or embedded program is in progress. 5. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. 6. v cc voltage requirements. 7. not 100% tested. parameter symbol parameter description (notes) test conditions min typ max unit i li input load current (note 1) v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9, acc input load current v cc = v cc max ; a9 = 12.5 v 35 a i lr reset leakage current v cc = v cc max ; reset# = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc initial read current (notes 2, 3) ce# = v il, oe# = v ih , 1 mhz 5 20 ma 5 mhz 18 25 10 mhz 35 50 i cc2 v cc intra-page read current (notes 2, 3) ce# = v il, oe# = v ih 10 mhz 5 20 ma 40 mhz 10 40 i cc3 v cc active write current (note 3) ce# = v il, oe# = v ih 50 60 ma i cc4 v cc standby current (note 3) ce#, reset# = v cc 0.3 v, wp# = v ih 15a i cc5 v cc reset current (note 3) reset# = v ss 0.3 v, wp# = v ih 15a i cc6 automatic sleep mode (notes 3, 5) v ih = v cc 0.3 v; -0.1< v il 0.3 v, wp# = v ih 15a v il input low voltage 1 (note 6) ?0.5 0.8 v v ih input high voltage 1 (note 6) 0.7 v cc v cc + 0.5 v v hh voltage for acc program acceleration v cc = 2.7 ?3.6 v 11.5 12.0 12.5 v v id voltage for autoselect and temporary sector unprotect v cc = 2.7 ?3.6 v 11.5 12.0 12.5 v v ol output low voltage (note 6) i ol = 4.0 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = ?2.0 ma, v cc = v cc min 0.85 v cc v v oh2 i oh = ?100 a, v cc = v cc min v cc ?0.4 v v lko low v cc lock-out voltage (note 7) 2.3 2.5 v
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 61 advance information test conditions note: diodes are in3064 or equivalent. figure 11. test setup table 12. test specifications 2.7 k ? c l 6.2 k ? 3.3 v device under tes t test condition all speeds unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0 or v cc v input timing measurement reference levels (see note) 0.5 v cc v output timing measurement reference levels 0.5 v cc v
62 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information key to switching waveforms figure 12. input waveforms and measurement levels waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) v cc 0.0 v output measurement level input 0.5 v cc 0.5 v cc
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 63 advance information ac characteristics read-only operations-s29gl064a only notes: 1. not 100% tested. 2. see figure 11 and table 12 for test specifications. figure 13. read operation timings parameter description te s t s e t u p speed options unit jedec std. 100 t avav t rc read cycle time (note 1) min 100 ns t avqv t acc address to output delay ce#, oe# = v il max 100 ns t elqv t ce chip enable to output delay oe# = v il max 100 ns t pacc page access time max 25 ns t glqv t oe output enable to output delay max 25 ns t ehqz t df chip enable to output high z (note 1) max 16 ns t ghqz t df output enable to output high z (note 1) max 16 ns t axqx t oh output hold time from a ddresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t oh t ce data we# addresses ce# oe# high z valid data high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df
64 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information note: shows device in word mode. addresses are a1?a-1 for byte mode . figure 14. page read timings hardware reset (reset#) note: not 100% tested . parameter description all speed options unit jedec std. t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# input low to standby mode (see note) min 20 s t rb ry/by# output high to ce#, oe# pin low min 0 ns a23 - a2 ce# oe# a1 - a0* data bus same page aa ab ac ad qa qb qc qd t acc t pac c t pac c t pac c
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 65 advance information figure 15. reset timings notes: 1. not 100% tested. 2. see the ?erase and programming perfor mance? section for more information. 3. for 1?16 words/1?32 bytes programmed. reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb
66 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information erase and program operations-s29gl064a only notes: 1. not 100% tested. 2. see the ?erase and programming perfor mance? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. if a program suspend command is issued within t poll , the device requires t poll before reading status data, once programming has resumed (that is, the program resume command has been wri tten). if the suspend command was issued after t poll , status data is available immediately after progra mming has resumed. see figure 16 . parameter speed options unit jedec std. description 100 t avav t wc write cycle time (note 1) min 100 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 35 ns t whdx t dh data hold time min 0 ns t ceph ce# high during toggle bit polling min 20 ns t oeph oe# high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 240 s single word program operation (note 2) typ 60 accelerated single word program operation (note 2) typ 54 t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t vhh v hh rise and fall time (note 1) min 250 ns t vcs v cc setup time (note 1) min 50 s t busy we# high to ry/by# low min 90 ns t poll program valid before status polling max 4 s
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 67 advance information notes: 1. pa = program address, pd = program data, d out is the true data at the program address. 2. illustration shows device in word mode. figure 16. program operation timings figure 17. accelerated program timing diagram oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t poll t cs status d out ry/by# t rb t busy t ch pa program command sequence (last two cycles) acc t vhh v hh v il or v ih v il or v ih t vhh acc t vhh v hh v il or v ih v il or v ih t vhh
68 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information notes: 1. sa = sector address (for sector erase), va = valid addr ess for reading status data (see ?write operation status?.) 2. illustration shows device in word mode. figure 18. chip/sector erase operation timings oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 69 advance information note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. figure 19. data# polling timings (during embedded algorithms) note: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. figure 20. toggle bit timings (during embedded algorithms) we# ce# oe# high z t oe high z dq7 dq0?dq6 ry/by# t busy complement tr u e addresses va t ch va va status data complement status data tr u e valid data valid data t poll t acc t ce t oeh t df t oh t rc oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6 / dq2 valid data valid status valid status valid status ry/by#
70 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information note: dq2 toggles only when read at an address within an erase-susp ended sector. the system may use oe# or ce# to toggle dq2 and dq6 . figure 21. dq2 vs. dq6 temporary sector unprotect notes: 1. not 100% tested. figure 22. temporary sector group unprotect timing diagram parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 s enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing reset# t vidr v id v il or v ih v id v il or v ih ce# we# ry/by# t vidr t rsp program or erase command sequence t rrb
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 71 advance information note: for sector group protect, a6:a0 = 0xx0010. for sector group unprotect, a6:a0 = 1xx0010. figure 23. sector group protect and unprotect timing diagram sector group protect: 150 s, sector group unprot ect: 15 ms 1 s reset# sa, a6, a3, a2, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector group protect or unprotect verify v id v ih
72 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information ac characteristics alternate ce# controlled erase and program operations-s29gl064a notes: 1. not 100% tested. 2. see the ?erase and programming perfor mance? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. if a program suspend command is issued within t poll , the device requires t poll before reading status data, once programming has resumed (that is, the program resume command has been wri tten). if the suspend command was issued after t poll , status data is available immediately after progra mming has resumed. see figure 24 . parameter speed options unit jedec std. description 100 t avav t wc write cycle time (note 1) min 100 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 35 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 35 ns t ehel t cph ce# pulse width high min 25 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 240 s single word program operation (note 2) typ 60 accelerated single word program operation (note 2) typ 54 t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t rh reset# high time before write min 50 ns t poll program valid before status polling (note 5) max 4 s
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 73 advance information notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sect or address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. 4. illustration shows device in word mode. figure 24. alternate ce# controlled write (erase/program) operation timings t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling pbd for program 55 for erase t rh t whwh1 or 2 t poll ry/by# t wh 29 for program buffer to flash 30 for sector erase 10 for chip erase pba for program 2aa for erase sa for program buffer to flash sa for sector erase 555 for chip erase t busy
74 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, v cc = 3.0v, 10,000 cycles; checkerboard data pattern. 2. under worst case conditions of 90 c; worst case v cc , 100,000 cycles. 3. effective programming time (typ) is 15 s (per word), 7.5 s (per byte). 4. effective accelerated progra mming time (typ) is 12.5 s (per word), 6.3 s (per byte). 5. effective write buffer specification is calculated on a per-wo rd/per-byte basis for a 16-word/ 32-byte write buffer operation. 6. in the pre-programming step of the embedded erase al gorithm, all bits are progra mmed to 00h before erasure. 7. system-level overhead is the time required to execute the command se quence(s) for the program command. see table 10 for further information on command definitions. parameter ty p ( n o t e 1 ) max (note 2) unit comments sector erase time 0.5 3.5 sec excludes 00h programming prior to erasure (note 6) chip erase time s29gl064a 64 128 total write buffer program time (notes 3 , 5 ) 240 s excludes system level overhead (note 7) total accelerated effective write buffer program time (notes 4 , 5 ) 200 s chip program time s29gl064a 63 sec
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 75 advance information psram type 1 4mbit (256k word x 16-bit) 8mbit (512k word x 16-bit) 16mbit (1m word x 16-bit) 32mbit (2m word x 16-bit) 64mbit (4m word x 16-bit) functional description absolute maximum ratings mode ce# ce2/zz# oe# we# ub# lb# addresses i/o 1-8 i/o 9-16 power read (word) l h l h l l x dout dout i active read (lower byte) l h l h h l x dout high-z i active read (upper byte) l h l h l h x high-z dout i active write (word) l h x l l l x din din i active write (lower byte) l h x l h l x din invalid i active write (upper byte) l h x l l h x invalid din i active outputs disabled l h h h x x x high-z high-z i active standby h h x x x x x high-z high-z i standby deep power down h l x x x x x high-z high-z i deep sleep item symbol ratings units voltage on any pin relative to v ss vin, vout -0.2 to v cc +0.3 v voltage on v cc relative to v ss v cc -0.2 to 3.6 v power dissipation p d 1 w storage temperature t stg -55 to 150 c operating temperature t a -25 to 85 c
76 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information dc characteristics ta b l e 1 3 . 4mb psram asynchronous asynchronous performance grade -70 density 4mb psram symbol parameter conditions min max units v cc power supply 2.7 3.3 v v ih input high level 0.8 vccq v cc + 0.3 v v il input low level -0.3 0.4 v i il input leakage current vin = 0 to v cc 0.5 a i lo output leakage current oe = v ih or chip disabled 0.5 a v oh output high voltage i oh = -1.0 ma v i oh = -0.2 ma 0.8 vccq i oh = -0.5 ma v ol output low voltage i ol = 2.0 ma v i ol = 0.2 ma 0.2 i ol = 0.5 ma i active operating current v cc = 3.3 v 25 ma i standby standby current v cc = 3.0 v 70 a v cc = 3.3 v i deep sleep deep power down current xa i par 1/4 1/4 array par current xa i par 1/2 1/2 array par current xa ta b l e 1 4 . 8mb psram asynchronous asynchronous version b c performance grade -55 -70 -70 density 8mb psram 8mb psram 8mb psram symbol parameter conditions min max units min max units min max units v cc power supply 2.7 3.3 v 2.7 3.6 v 2.7 3.3 v v ih input high level 2.2 v cc + 0.3 v 2.2 v cc + 0.3 v 0.8 v cc +0.3 v v il input low level -0.3 0.6 v -0.3 0.6 v -0.3 0.4 v i il input leakage current vin = 0 to v cc 0.5 a 0.5 a 0.5 a i lo output leakage current oe = v ih or chip disabled 0.5 a 0.5 a 0.5 a
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 77 advance information v oh output high voltage i oh = -1.0 ma v cc -0.4 v v cc -0.4 vv i oh = -0.2 ma 0.8 v ccq i oh = -0.5 ma v ol output low voltage i ol = 2.0 ma 0.4 v 0.4 vv i ol = 0.2 ma 0.2 i ol = 0.5 ma i active operating current v cc = 3.3 v 25 ma 23 ma 25 ma i standby standby current v cc = 3.0 v 60 a 60 a 70 a v cc = 3.3 v i deep sleep deep power down current xa xa xa i par 1/4 1/4 array par current xa xa xa i par 1/2 1/2 array par current xa xa xa ta b l e 1 5 . 16mb psram asynchronous asynchronous performance grade -55 -70 density 16mb psram 16mb psram symbol parameter conditions minimum maximum units minimum maximum units v cc power supply 2.7 3.6 v 2.7 3.6 v v ih input high level 2.2 v cc + 0.3 v 2.2 v cc + 0.3 v v il input low level -0.3 0.6 v -0.3 0.6 v i il input leakage current vin = 0 to v cc 0.5 a 0.5 a i lo output leakage current oe = v ih or chip disabled 0.5 a 0.5 a v oh output high voltage i oh = -1.0 ma v cc -0.4 v v cc -0.4 v i oh = -0.2 ma i oh = -0.5 ma v ol output low voltage i ol = 2.0 ma 0.4 v 0.4 v i ol = 0.2 ma i ol = 0.5 ma i active operating current v cc = 3.3 v 25 ma 25 ma i standby standby current v cc = 3.0 v 100 a 100 a v cc = 3.3 v i deep sleep deep power down current x a x a i par 1/4 1/4 array par current x a x a table 14. 8mb psram asynchronous (continued) asynchronous version b c performance grade -55 -70 -70 density 8mb psram 8mb psram 8mb psram symbol parameter conditions min max units min max units min max units
78 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information i par 1/2 1/2 array par current x a x a ta b l e 1 6 . 16mb psram page mode page mode performance grade -60 -65 -70 density 16mb psram 16mb psram 16mb psram symbol parameter conditions min max units min max units min max units v cc power supply 2.7 3.3 v 2.7 3.3 v 2.7 3.3 v v ih input high level 0.8 vccq v cc + 0.2 v 0.8 vccq v cc + 0.2 v 0.8 vccq v cc + 0.2 v v il input low level -0.2 0.2 vccq v -0.2 0.2 vccq v -0.2 0.2 vccq v i il input leakage current vin = 0 to v cc 1a 1a 1a i lo output leakage current oe = v ih or chip disabled 1a 1a 1a v oh output high voltage i oh = -1.0 ma vv v i oh = -0.2 ma i oh = -0.5 ma 0.8 vccq 0.8 vccq 0.8 vccq v ol output low voltage i ol = 2.0 ma vv v i ol = 0.2 ma i ol = 0.5 ma 0.2 vccq 0.2 vccq 0.2 vccq i active operating current v cc = 3.3 v 25 ma 25 ma 25 ma i standby standby current v cc = 3.0 v a a a v cc = 3.3 v 100 100 100 i deep sleep deep power down current 10 a 10 a 10 a i par 1/4 1/4 array par current 65 a 65 a 65 a i par 1/2 1/2 array par current 80 a 80 a 80 a table 15. 16mb psram asynchronous (continued) asynchronous performance grade -55 -70 density 16mb psram 16mb psram symbol parameter conditions minimum maximum units minimum maximum units
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 79 advance information ta b l e 1 7 . 32mb psram page mode page mode version c e performance grade -65 -60 -65 -70 density 32mb psram 32mb psram 32mb psram 32mb psram symbol parameter conditions min max units min max units min max units min max units v cc power supply 2.7 3.6 v 2.7 3.3 v 2.7 3.3 v 2.7 3.3 v v ih input high level 1.4 v cc + 0.2 v0.8 vccq v cc + 0.2 v0.8 vccq v cc + 0.2 v 0.8 vccq v cc + 0.2 v v il input low level -0.2 0.4 v -0.2 0.2 vccq v-0.2 0.2 vccq v-0.2 0.2 vccq v i il input leakage current vin = 0 to v cc 0.5 a 1 a 1 a 1 a i lo output leakage current oe = v ih or chip disabled 0.5 a 1 a 1 a 1 a v oh output high voltage i oh = -1.0 ma vv vv i oh = -0.2 ma 0.8 vccq i oh = -0.5 ma 0.8 vccq 0.8 vccq 0.8 vccq v ol output low voltage i ol = 2.0 ma vv vv i ol = 0.2 ma 0.2 i ol = 0.5 ma 0.2 vccq 0.2 vccq 0.2 vccq i active operating current v cc = 3.3 v 25 ma 25 ma 25 ma 25 ma i standby standby current v cc = 3.0 v a a a a v cc = 3.3 v 100 120 120 120 i deep sleep deep power down current 10 a 10 a 10 a 10 a i par 1/4 1/4 array par current 65 a 75 a 75 a 75 a i par 1/2 1/2 array par current 80 a 90 a 90 a 90 a ta b l e 1 8 . 64mb psram page mode page mode performance grade -70 density 64mb psram symbol parameter conditions min max units v cc power supply 2.7 3.3 v v ih input high level 0.8 vccq v cc + 0.2 v v il input low level -0.2 0.2 vccq v
80 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information timing test conditions i il input leakage current vin = 0 to v cc 1a i lo output leakage current oe = v ih or chip disabled 1a v oh output high voltage i oh = -1.0 ma v i oh = -0.2 ma i oh = -0.5 ma 0.8 vccq v ol output low voltage i ol = 2.0 ma v i ol = 0.2 ma i ol = 0.5 ma 0.2 vccq i active operating current v cc = 3.3 v 25 ma i standby standby current v cc = 3.0 v a v cc = 3.3 v 120 i deep sleep deep power down current 10 a i par 1/4 1/4 array par current 65 a i par 1/2 1/2 array par current 80 a item input pulse level 0.1 v cc to 0.9 v cc input rise and fall time 5ns input and output timing reference levels 0.5 v cc operating temperature -25c to +85c table 18. 64mb psram page mode (continued) page mode performance grade -70 density 64mb psram symbol parameter conditions min max units
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 81 advance information output load circuit power up sequence after applying power, maintain a stable power supply for a minimum of 200 s after ce# > v ih . figure 25. output load circuit v cc 30 pf i/o 14.5k 14.5k output load
82 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information ac characteristics ta b l e 1 9 . 4mb psram page mode asynchronous performance grade -70 density 4mb psram 3 volt symbol parameter min max units read trc read cycle time 70 ns taa address access time 70 ns tco chip select to output 70 ns toe output enable to valid output 20 ns tba ub#, lb# access time 70 ns tlz chip select to low-z output 10 ns tblz ub#, lb# enable to low-z output 10 ns tolz output enable to low-z output 5ns thz chip enable to high-z output 020ns tbhz ub#, lb# disable to high-z output 020ns tohz output disable to high-z output 020ns toh output hold from address change 10 ns
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 83 advance information write twc write cycle time 70 ns tcw chipselect to end of write 70 ns tas address set up time 0ns taw address valid to end of write 70 ns tbw ub#, lb# valid to end of write 70 ns twp write pulse width 55 ns twr write recovery time 0ns twhz write to output high-z 20 ns tdw data to write time overlap 25 ns tdh data hold from write time 0ns tow end write to output low-z 5 tow write high pulse width 7.5 ns other tpc page read cycle x tpa page address access time x twpc page write cycle x tcp chip select high pulse width x table 19. 4mb psram page mode (continued) asynchronous performance grade -70 density 4mb psram 3 volt symbol parameter min max units
84 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information ta b l e 2 0 . 8mb psram asynchronous asynchronous version b c performance grade -55 -70 -70 density 8mb psram 8mb psram 8mb psram 3 volt symbol parameter min max units min max units min max units read trc read cycle time 55 ns 70 ns 70 ns taa address access time 55 ns 70 ns 70 ns tco chip select to output 55 ns 70 ns 70 ns toe output enable to valid output 30 ns 35 ns 20 ns tba ub#, lb# access time 55 ns 70 ns 70 ns tlz chip select to low-z output 5 ns 5 ns 10 ns tblz ub#, lb# enable to low-z output 5 ns 5 ns 10 ns tolz output enable to low-z output 5ns5ns5ns thz chip enable to high-z output 020ns025ns 020ns tbhz ub#, lb# disable to high-z output 020ns025ns 020ns tohz output disable to high-z output 020ns025ns 020ns toh output hold from address change 10 ns 10 ns 10 ns
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 85 advance information write twc write cycle time 55 ns 70 ns 70 ns tcw chip select to end of write 45 ns 55 ns 70 ns tas address set up time 0ns0ns0ns taw address valid to end of write 45 ns 55 ns 70 ns tbw ub#, lb# valid to end of write 45 ns 55 ns 70 ns twp write pulse width 45 ns 55 ns 55 ns twr write recovery time 0ns0ns0ns twhz write to output high-z 25 ns 25 20 ns tdw data to write time overlap 40 ns 40 ns 25 ns tdh data hold from write time 0ns0ns0ns tow end write to output low-z 555 tow write high pulse width xxnsxxnsxxns other tpc page read cycle x x x tpa page address access time xxx twpc page write cycle x x x tcp chip select high pulse width xxx table 20. 8mb psram asynchronous (continued) asynchronous version b c performance grade -55 -70 -70 density 8mb psram 8mb psram 8mb psram 3 volt symbol parameter min max units min max units min max units
86 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information figure 26. 16mb psram asynchronous asynchronous performance grade -55 -70 density 16mb psram 16mb psram 3 volt symbol parameter min max units min max units read trc read cycle time 55 ns 70 ns taa address access time 55 ns 70 ns tco chip select to output 55 ns 70 ns toe output enable to valid output 30 ns 35 ns tba ub#, lb# access time 55 ns 70 ns tlz chip select to low-z output 5ns5ns tblz ub#, lb# enable to low-z output 5ns5ns tolz output enable to low-z output 5ns5ns thz chip enable to high-z output 025ns025ns tbhz ub#, lb# disable to high-z output 025ns025ns tohz output disable to high-z output 025ns025ns toh output hold from address change 10 ns 10 ns write twc write cycle time 55 ns 70 ns tcw chipselect to end of write 50 ns 55 ns tas address set up time 0ns0ns taw address valid to end of write 50 ns 55 ns tbw ub#, lb# valid to end of write 50 ns 55 ns twp write pulse width 50 ns 55 ns twr write recovery time 0ns0ns twhz write to output high-z 25 ns 25 ns tdw data to write time overlap 25 ns 25 ns tdh data hold from write time 0ns0ns tow end write to output low-z 55 tow write high pulse width xxnsxxns
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 87 advance information other tpc page read cycle x x tpa page address access time xx twpc page write cycle x x tcp chip select high pulse width xx ta b l e 2 1 . 16mb psram page mode page mode performance grade -60 -65 -70 density 16mb psram 16mb psram 16mb psram 3 volt symbol parameter min max units min max units min max units read trc read cycle time 60 20k ns 65 20k ns 70 20k ns taa address access time 60 ns 65 ns 70 ns tco chip select to output 60 ns 65 ns 70 ns toe output enable to valid output 25 ns 25 ns 25 ns tba ub#, lb# access time 60 ns 65 ns 70 ns tlz chip select to low-z output 10 ns 10 ns 10 ns tblz ub#, lb# enable to low-z output 10 ns 10 ns 10 ns tolz output enable to low-z output 5ns5ns5ns thz chip enable to high-z output 05ns05ns05ns tbhz ub#, lb# disable to high-z output 05ns05ns05ns tohz output disable to high-z output 05ns05ns05ns toh output hold from address change 5ns5ns5ns figure 26. 16mb psram asynchronous (continued) asynchronous performance grade -55 -70 density 16mb psram 16mb psram 3 volt symbol parameter min max units min max units
88 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information write twc write cycle time 60 20k ns 65 20k ns 70 20k ns tcw chipselect to end of write 50 ns 60 ns 60 ns tas address set up time 0ns0ns0ns taw address valid to end of write 50 ns 60 ns 60 ns tbw ub#, lb# valid to end of write 50 ns 60 ns 60 ns twp write pulse width 50 ns 50 ns 50 ns twr write recovery time 0ns0ns0ns twhz write to output high-z 5ns 5ns 5ns tdw data to write time overlap 20 ns 20 ns 20 ns tdh data hold from write time 0ns0ns0ns tow end write to output low-z 555 tow write high pulse width 7.5 ns 7.5 ns 7.5 ns other tpc page read cycle 25 20k ns 25 20k ns 25 20k ns tpa page address access time 25 ns 25 ns 25 ns twpc page write cycle 25 20k ns 25 20k ns 25 20k ns tcp chip select high pulse width 10 ns 10 ns 10 ns table 21. 16mb psram page mode (continued) page mode performance grade -60 -65 -70 density 16mb psram 16mb psram 16mb psram 3 volt symbol parameter min max units min max units min max units
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 89 advance information table 22. 32mb psram page mode page mode version c e performance grade -65 -60 -65 -70 density 32mb psram 32mb psram 32mb psram 32mb psram 3 volt symbol parameter min max units min max units min max units min max units read trc read cycle time 65 20k ns 60 20k ns 65 20k ns 70 20k ns taa address access time 65 ns 60 ns 65 ns 70 ns tco chip select to output 65 ns 60 ns 65 ns 70 ns toe output enable to valid output 20 ns 25 ns 25 ns 25 ns tba ub#, lb# access time 65 ns 60 ns 65 ns 70 ns tlz chip select to low-z output 10 ns 10 ns 10 ns 10 ns tblz ub#, lb# enable to low-z output 10 ns 10 ns 10 ns 10 ns tolz output enable to low-z output 5 ns 5 ns 5 ns 5 ns thz chip enable to high-z output 020ns 0 5 ns 0 5ns 0 5ns tbhz ub#, lb# disable to high-z output 020ns 0 5 ns 0 5ns 0 5ns tohz output disable to high-z output 020ns 0 5 ns 0 5ns 0 5ns toh output hold from address change 5 ns 5 ns 5 ns 5 ns
90 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information write twc write cycle time 65 20k ns 60 20k ns 65 20k ns 70 20k ns tcw chipselect to end of write 55 ns 50 ns 60 ns 60 ns tas address set up time 0 ns 0 ns 0 ns 0 ns taw address valid to end of write 55 ns 50 ns 60 ns 60 ns tbw ub#, lb# valid to end of write 55 ns 50 ns 60 ns 60 ns twp write pulse width 55 20k ns 50 ns 50 ns 50 ns twr write recovery time 0 ns 0 ns 0 ns 0 ns twhz write to output high-z 5 ns 5 ns 5 ns 5 ns tdw data to write time overlap 25 ns 20 ns 20 ns 20 ns tdh data hold from write time 0 ns 0 ns 0 ns 0 ns tow end write to output low-z 55 5 5 tow write high pulse width 7.5 ns 7.5 ns 7.5 ns 7.5 ns other tpc page read cycle 25 20k ns 25 20k ns 25 20k ns 25 20k ns tpa page address access time 25 ns 25 ns 25 ns 25 ns twpc page write cycle 25 20k ns 25 20k ns 25 20k ns 25 20k ns tcp chip select high pulse width 10 ns 10 ns 10 ns 10 ns table 22. 32mb psram page mode (continued) page mode version c e performance grade -65 -60 -65 -70 density 32mb psram 32mb psram 32mb psram 32mb psram 3 volt symbol parameter min max units min max units min max units min max units
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 91 advance information ta b l e 2 3 . 64mb psram page mode page mode performance grade -70 density 64mb psram 3 volt symbol parameter min max units read trc read cycle time 70 20k ns taa address access time 70 ns tco chip select to output 70 ns toe output enable to valid output 25 ns tba ub#, lb# access time 70 ns tlz chip select to low-z output 10 ns tblz ub#, lb# enable to low-z output 10 ns tolz output enable to low-z output 5ns thz chip enable to high-z output 05ns tbhz ub#, lb# disable to high-z output 05ns tohz output disable to high-z output 05ns toh output hold from address change 5ns write twc write cycle time 70 20k ns tcw chipselect to end of write 60 ns tas address set up time 0ns taw address valid to end of write 60 ns tbw ub#, lb# valid to end of write 60 ns twp write pulse width 50 20k ns twr write recovery time 0ns twhz write to output high-z 5ns tdw data to write time overlap 20 ns tdh data hold from write time 0ns tow end write to output low-z 5 tow write high pulse width 7.5 ns
92 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information timing diagrams read cycle other tpc page read cycle 20 20k ns tpa page address access time 20 ns twpc page write cycle 20 20k ns tcp chip select high pulse width 10 ns figure 27. timing of read cycle (ce# = oe# = v il , we# = zz# = v ih ) table 23. 64mb psram page mode (continued) page mode performance grade -70 density 64mb psram 3 volt symbol parameter min max units a ddress data out t rc t aa t oh data valid previous data valid
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 93 advance information figure 28. timing waveform of read cycle (we# = zz# = v ih ) address lb#, ub# oe# data valid t rc t aa t co t hz t ohz t bhz t olz t oe t lz high-z data out t lb, t ub t blz ce#
94 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information figure 29. timing waveform of page mode read cycle (we# = zz# = v ih ) page address (a4 - a20) lb#, ub# oe# t aa t co t hz t ohz t bhz t olz t oe high-z data out t lb, t ub t blz, ce# word address (a0 - a3) t pa t rc t pgmax t pc
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 95 advance information write cycle figure 30. timing waveform of write cycle (we# control, zz# = v ih ) figure 31. timing waveform of write cy cle (ce# control, zz# = v ih ) addr es s dat a in ce# data valid t wc t aw t cw t wr t whz t dh high-z we# da ta out high-z t ow t as t wp t dw t bw lb#, ub# ad dr es s we# data valid t wc t aw t cw t wr t dh lb#, ub# dat a in high-z t as t wp t dw t bw da ta o ut t whz ce#
96 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information power savings modes (for 16m page mode, 32m and 64m only) there are several power savings modes. ? partial array self refresh ? temperature compensated refresh (64m) ? deep sleep mode ? reduced memory size (32m, 16m) the operation of the power saving modes ins controlled by the settings of bits contained in the mode register. this defini tion of the mode register is shown in figure 33 and the various bits are used to enable and disable the various low power modes as well as enabling page mo de operation. the mode register is set by using the timings defined in figure 34 . partial array self refresh (par) in this mode of operation, the internal refresh operation can be restricted to a 16mb, 32mb, or 48mb portion of the array. the array partition to be refreshed is determined by the respective bit settings in the mode register. the register set - figure 32. timing waveform of page mode write cycle (zz# = v ih ) page a ddr es s (a4 - a 20) lb#, ub# we# t wp t cw t dw high-z dat a out t lbw, t ubw ce# wor d a ddr es s (a0 - a3 ) t wc t pwc t dh t pdw t pdh t pdw t pdh t as t pgmax
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 97 advance information tings for the pasr operation are defined in ta b l e 2 5 . in this pasr mode, when zz# is active low, only the portion of th e array that is set in the register is re - freshed. the data in the remainder of th e array will be lost. the pasr operation mode is only available during standby ti me (zz# low) and once zz# is returned high, the device resumes full array refresh. all future pasr cycles will use the contents of the mode register that has been previously set. to change the ad - dress space of the pasr mode, the mode register must be reset using the previously defined procedures. for pasr to be activated, the register bit, a4 must be set to a one (1) value, ?pasr enabled?. if this is the case, pasr will be acti - vated 10 s after zz# is brought low. if the a4 register bit is set equal to zero (0), pasr will not be activated. temperature compensated refresh (for 64mb) in this mode of operation, the internal refresh rate can be optimized for the op - eration temperature used and this can then lower standby current. the dram array in the psram must be refreshed inte rnally on a regular basis. at higher temperatures, the dram cell must be re freshed more often than at lower tem - peratures. by setting the temperature of operation in the mode register, this refresh rate can be optimized to yield the lowest standby current at the given op - erating temperature. there are four different temperature settings that can be programmed in to the psram. these are defined in figure 33 . deep sleep mode in this mode of operation, the internal re fresh is turned off and all data integrity of the array is lost. deep sleep is entered by bringing zz# low with the a4 reg - ister bit set to a zero (0), ?deep sleep enabled?. if this is the case, deep sleep will be entered 10 s after zz# is brought low. the device will remain in this mode as long as zz# remains low. if the a4 re gister bit is set equal to one (1), deep sleep will not be activated. reduced memory size (for 32m and 16m) in this mode of operation, the 32mb psram can be operated as a 8mb or 16mb device. the mode and array size are determ ined by the settings in the va register. the va register is set according to the following timings and the bit settings in the table ?address patterns for rms?. the rms mode is enabled at the time of zz transitioning high and the mode remain s active until the register is updated. to return to the full 32mb address space, the va register must be reset using the previously defined procedures. while op erating in the rms mode, the unselected portion of the array may not be used. other mode register settings (for 64m) the page mode operation can also be en abled and disabled using the mode reg - ister. register bit a7 controls the operation of page mode and setting this bit to a one (1), enables page mode. if the register bit a7 is set to a zero (0), page mode operation is disabled.
98 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information figure 33. mode register figure 34. mode register updatetimings (ub#, lb#, oe# are don?t care) deep sleep enable/disabl e 0 = deep sleep enabled 1 = deep sleep disabled (default) par section 1 1 1 = top 1/4 array 1 1 0 = top 1/2 array 1 0 1 = top 3/4 array 1 0 0 = no par 0 1 1 = bottom 1/4 array 0 1 0 = bottom 1/2 array 0 0 1 = bottom 3/4 array 0 0 0 = full array (default) reserved must set to all 0 a21 - a8 a7 a6 a5 a4 a3 a2 a1 a0 page mode 0 = page mode disabled (default) 1 = page mode enabled te m p compensated refresh 1 0 = 15 o c 0 1 = 45 o c 0 0 = 70 o c 1 1 = 85 o c (default) array mode for zz# 0 = par (default) 1 = rms 64 mb 32 mb / 16 mb address zz# t wc t as ce# we# t zzwe t aw t wp t wr t cdzz
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 99 advance information notes: 1. minimum cycle time for writing register is equal to speed grade of product. figure 35. deep sleep mode - entry/exit timings (for 64m) figure 36. deep sleep mode - entry/exit timings (for 32m and 16m) ta b l e 2 4 . mode register update and deep sleep timings item symbol min max unit note chip deselect to zz# low t cdzz 5 ns zz# low to we# low t zzwe 10 500 ns write register cycle time t wc 70/85 ns 1 chip enable to end of write t cw 70/85 ns 1 address valid to end of write t aw 70/85 ns 1 write recovery time t wr 0 ns address setup time t as 0 ns write pulse width t wr 40 ns deep sleep pulse width t zzmin 10 s deep sleep recovery t r 200 s ta b l e 2 5 . address patterns for pasr (a4=1) (64m) a2 a1 a0 active section address space size density 1 1 1 top quarter of die 300000h-3fffffh 1mb x 16 16mb 1 1 0 top half of die 200000h-3fffffh 2mb x 16 32mb 1 0 1 reserved zz# t zzmin t cdzz t r ce# a4 zz# t wc t bw t as ce# we# t zzwe t aw t wp t wr t r t zzmin lb#, ub#
100 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information icc characteristics 1 0 0 no pasr none 0 0 0 1 1 bottom quarter of die 000000h-0fffffh 1mb x 16 16mb 0 1 0 bottom half of die 000000h-1fffffh 2mb x 16 32mb 0 0 1 reserved 0 0 0 full array 000000h-3fffffh 4mb x 16 64mb ta b l e 2 6 . deep icc characteristics (for 64mb) item symbol te s t array partition ty p max unit pasr mode standby current i pasr v in = v cc or 0v, chip disabled, t a = 85c none 10 a 1/4 array 60 1/2 array 80 full array 120 item symbol max temperature ty p max unit temperature compensated refresh current i tcr 15c 50 a 45c 60 70c 80 85c 120 item symbol te s t ty p max unit deep sleep current i zz v in = v cc or 0v, chip in zz# mode, t a = 25c 10 a ta b l e 2 7 . address patterns for par (a3= 0, a4=1) (32m) a2 a1 a0 active section address space size density 0 1 1 one-quarter of die 000000h - 07ffffh 512kb x 16 8mb 0 1 0 one-half of die 000000h - 0fffffh 1mb x 16 16mb x 0 0 full die 000000h - 1fffffh 2mb x 16 32mb 1 1 1 one-quarter of die 180000h - 1fffffh 512kb x 16 8mb 1 1 0 one-half of die 100000h - 1fffffh 1mb x 16 16mb ta b l e 2 8 . address patterns for rms (a3 = 1, a4 = 1) (32m) a2 a1 a0 active section address space size density 0 1 1 one-quarter of die 000000h - 07ffffh 512kb x 16 8mb 0 1 0 one-half of die 000000h - 0fffffh 1mb x 16 16mb table 25. address patterns for pasr (a4=1) (64m) (continued) a2 a1 a0 active section address space size density
february 8, 2005 s71gl064a_00_a2 s71gl064a based mcps 101 advance information 1 1 1 one-quarter of die 180000h - 1fffffh 512kb x 16 8mb 1 1 0 one-half of die 100000h - 1fffffh 1mb x 16 16mb ta b l e 2 9 . low power icc characteristics (32m) item symbol te s t array partition ty p max unit par mode standby current i par v in = v cc or 0v, chip disabled, t a = 85 o c 1/4 array 75 a 1/2 array 90 a rms mode standby current i rmssb v in = v cc or 0v, chip disabled, t a = 85 o c 8mb device 75 a 16mb device 90 a deep sleep current i zz v in = v cc or 0v, chip in zz mode, t a = 85 o c 10 a ta b l e 3 0 . address patterns for par (a3= 0, a4=1) (16m) a2 a1 a0 active section address space size density 0 1 1 one-quarter of die 00000h - 0ffffh 256kb x 16 4mb 0 1 0 one-half of die 00000h - 7ffffh 512kb x 16 8mb x 0 0 full die 00000h - fffffh 1mb x 16 16mb 1 1 1 one-quarter of die c0000h - ffffh 256kb x 16 4mb 1 1 0 one-half of die 80000h - 1fffffh 512kb x 16 8mb ta b l e 3 1 . address patterns for rms (a3 = 1, a4 = 1) (16m) a2 a1 a0 active section address space size density 0 1 1 one-quarter of die 00000h - 0ffffh 256kb x 16 4mb 0 1 0 one-half of die 00000h - 7ffffh 512kb x 16 8mb 1 1 1 one-quarter of die c0000h - fffffh 256kb x 16 4mb 1 1 0 one-half of die 80000h - fffffh 512kb x 16 8mb ta b l e 3 2 . low power icc characteristics (16m) item symbol te s t array partition ty p max unit par mode standby current i par v in = v cc or 0v, chip disabled, t a = 85 o c 1/4 array 65 a 1/2 array 80 rms mode standby current i rmssb v in = v cc or 0v, chip disabled, t a = 85 o c 4mb device 65 a 8mb device 80 deep sleep current i zz v in = v cc or 0v, chip in zz# mode, t a = 85 o c 10 a table 28. address patterns for rms (a3 = 1, a4 = 1) (32m) (continued) a2 a1 a0 active section address space size density
102 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information psram type 7 16mb (1m word x 16-bit) 32mb (2m word x 16-bit) 64mb (4m word x 16-bit) cmos 1m/2m/4m-word x 16-bit fast cyc le random access memory with low power sram interface features ? asynchronous sram interface ? fast access time ? tce = taa = 60ns max (16m) ? tce = taa = 65ns max (32m/64m) ? 8 words page access capability ? tpaa = 20ns max (32m/64m) ? low voltage operating condition ? vdd = +2.7v to +3.1v ? wide operating temperature ? ta = -30c to +85c ? byte control by lb and ub ? various power down modes ? sleep (16m) ? sleep, 4m-bit partial, or 8m-bit partial (32m) ? sleep, 8m-bit partial, or 16m-bit partial (64m) pin description pin name description a 21 to a 0 address input: a 19 to a 0 for 16m, a 20 to a 0 for 32m, a 21 to a 0 for 64m ce1# chip enable (low active) ce2# chip enable (high active) we# write enable (low active) oe# output enable (low active) ub# upper byte control (low active) lb# lower byte control (low active) dq 16 - 9 upper byte data input/output dq 8 - 1 lower byte data input/output v dd power supply v ss ground
february 8, 2005 s71gl064a_00_a2 psram type 7 103 advance information functional description legend: l = v il , h = v ih , x can be either v il or v ih , high-z = high impedance. notes: 1. should not be kept this logic condition longer than 1 ms. please contact local spansion representative for the relaxation of 1ms limitation. 2. power down mode can be entered from standby state and all dq pins are in high-z state. data retention depends on the selection of the power-down program, 16m has data retentio n in all modes except power down. refer to power down for details. 3. can be either v il or v ih but must be valid before read or write. power down (for 32m, 64m only) power down the power down is a low-power idle state controlled by ce2. ce2 low drives the device in power-down mode and maintain s the low-power idle state as long as ce2 is kept low. ce2 high resumes th e device from power-down mode. these devices have three power-down modes. these can be programmed by series of read/write operation. each mode has following features. the default state is sleep and it is the lowest power consumpt ion but all data is lost once ce2 is brought to low for power down. it is not required to program to sleep mode after power-up. mode ce2# ce1# we# oe# lb# ub# a 21-0 dq 8-1 dq 16-9 standby (deselect) h h x x x x x high-z high-z output disable (note 1) hl hhxx note 3 high-z high-z output disable (no read) hl h h valid high-z high-z read (upper byte) h l valid high-z output valid read (lower byte) l h valid output valid high-z read (word) l l valid output valid output valid no write lh h h valid invalid invalid write (upper byte) h l valid invalid input valid write (lower byte) l h valid input valid invalid write (word) l l valid input valid input valid power down lxxxxx x high-z high-z 32m 64m mode retention data retention address mode retention data retention address sleep (default) no n/a sleep (default) no n/a 4m partial 4m bit 00000h to 3ffffh 8m partial 8m bit 00000h to 7ffffh 8m partial 8m bit 00000h to 7ffffh 16m partial 16m bit 00000h to fffffh
104 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information power down program sequence the program requires 6 read/write operations with a unique address. between each read/write operation requires that device be in standby mode. the following table shows the detail sequence. the first cycle reads from the most significant address (msb). the second and third cycle are to write ba ck the data (rda) read by first cycle. if the second or third cycle is written in to the different address, the program is cancelled, and the data wri tten by the second or third cycle is valid as a normal write operation. the fourth and fifth cycles write to msb. the data from the fourth and fifth cycles is ?don?t care.? if the fourth or fifth cycles are written into different address, the program is also cancelled but write data might not be written as normal write operation. the last cycle is to read from specific address key for mode selection. once this program sequence is performed from a partial mode to the other partial mode, the written data stored in memory ce ll array can be lost. so, it should per - form this program prior to regular read/w rite operation if partial mode is used. address key the address key has following format. cycle # operation address data 1st read 3fffffh (msb) read data (rda) 2nd write 3fffffh rda 3rd write 3fffffh rda 4th write 3fffffh don?t care (x) 5th write 3fffffh x 6th read address key read data (rdb) mode address 32m 64m a21 a20 a19 a18 - a0 binary sleep (default) sleep (default) 1 1 1 1 3fffffh 4m partial n/a 1 1 0 1 37ffffh 8m partial 8m partial 1 0 1 1 2fffffh n/a 16m partial 1 0 0 1 27ffffh
february 8, 2005 s71gl064a_00_a2 psram type 7 105 advance information absolute maximum ratings warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. recommended operating conditions (see warning below) notes: 1. maximum dc voltage on input and i/o pins is v dd +0.2v. during voltage transitions, inputs can positive overshoot to v dd +1.0v for periods of up to 5 ns. 2. minimum dc voltage on input or i/o pins is -0.3v. during voltage transitions, inputs can negative overshoot v ss to -1.0v for periods of up to 5ns. warning: recommended operating conditions are normal operating ranges for th e semiconductor device. all the de- vice?s electrical characteristics are warr anted when operated within these ranges. always use semiconductor devices within the recommended operating conditions . operation outside these ranges can adversely affect reliability and could result in device failure. no warranty is made with respect to us es, operating conditions, or combinatio ns not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fu jitsu representative before- hand. package capacitance test conditions: t a = 25c, f = 1.0 mhz item symbol value unit voltage of v dd supply relative to v ss v dd -0.5 to +3.6 v voltage at any pin relative to v ss v in , v out -0.5 to +3.6 v short circuit output current i out 50 ma storage temperature t stg -55 to +125 c parameter symbol min max unit supply voltage v dd 2.7 3.1 v v ss 0 0 v high level input voltage (note 1) v ih v dd 0.8 v dd +0.2 v high level input voltage (note 1) v il -0.3 v dd 0.2 v ambient temperature t a -30 85 c symbol description te s t s e t u p ty p max unit c in1 address input capacitance v in = 0v ? 5 pf c in2 control input capacitance v in = 0v ? 5 pf c io data input/output capacitance v io = 0v ? 8 pf
106 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information dc characteristics (under recommended condition s unless otherwise noted) notes: 1. all voltages are referenced to v ss . 2. dc characteristics are measured after following power-up timing. 3. i out depends on the output load conditions. parameter symbol test conditions 16m 32m 64m unit min. max. min. max. min. max. input leakage current i li v in = v ss to v dd -1.0 +1.0 -1.0 +1.0 -1.0 +1.0 a output leakage current i lo v out = v ss to v dd , output disable -1.0 +1.0 -1.0 +1.0 -1.0 +1.0 a output high voltage level v oh v dd = v dd (min), i oh = ?0.5ma 2.2 ? 2.4 ? 2.4 ? v output low voltage level v ol i ol = 1ma ? 0.4 ? 0.4 ? 0.4 v v dd power down current i ddps v dd = v dd max., v in = v ih or v il , ce2 0.2 v sleep 10 ? 10 ? 10 a i ddp4 4m partial n/a ? 40 n/a a i ddp8 8m partial n/a ? 50 ? 80 a i ddp16 16m partial n/a n/a ? 100 a v dd standby current i dds v dd = v dd max., v in = v ih or v il ce 1 = ce2 = v ih ? 1 ? 1.5 ? 1.5 ma i dds1 v dd = v dd max., v in 0.2v or v in v dd ? 0.2v, ce 1 = ce2 v dd ? 0.2v ta< + 85 c ? 100 ? 80 ? 170 a ta< + 40 c 90 a v dd active current i dda1 v dd = v dd max., v in = v ih or v il , ce 1 = v il and ce2= v ih , i out =0ma t rc / t wc = min. ? 20 ? 30 ? 40 ma i dda2 t rc / t wc = 1 s ? 3 ? 3 ? 5 ma v dd page read current i dda3 v dd = v dd max., v in = v ih or v il , ce 1 = v il and ce2= v ih , i out =0ma, t prc = min. n/a ? 10 ? 10 ma
february 8, 2005 s71gl064a_00_a2 psram type 7 107 advance information ac characteristics (under recommended operating co nditions unless otherwise noted) read operation notes: 1. maximum value is applicable if ce#1 is kept at low without change of address input of a3 to a21. if needed by system operation, please contact local spansion representative for the relaxation of 1s limitation. 2. address should not be changed within minimum t rc . 3. the output load 50 pf wi th 50 ohm termination to v dd x 0.5 (16m), the output load 50 pf (32m and 64m). 4. the output load 5pf. 5. applicable to a3 to a21 (32m an d 64m) when ce1# is kept at low. 6. applicable only to a0, a1 and a2 (32m and 64m) when ce1# is kept at low fo r the page address access. 7. in case page read cycle is continued with keeping ce1# stay s low, ce1# must be brought to high within 4 s. in other words, page read cycle must be closed within 4 s. 8. applicable when at least two of address inputs among applicable are switched from previous state. 9. t rc (min) and t prc (min) must be satisfied. 10. if actual value of t whol is shorter than specified minimum values, the actual t aa of following read can become longer by the amount of subtracting the actual value from the specified minimum value. parameter symbol 16m 32m 64m unit notes min. max. min. max. min. max. read cycle time t rc 70 1000 65 1000 65 1000 ns 1, 2 ce1# access time t ce ?60?65?65ns 3 oe# access time t oe ?40?40?40ns 3 address access time t aa ?60?65?65ns 3, 5 lb# / ub# access time t ba ?30?30?30ns 3 page address access time t paa n/a ? 20 ? 20 ns 3,6 page read cycle time t prc n/a 20 1000 20 1000 ns 1, 6, 7 output data hold time t oh 5?5?5?ns 3 ce1# low to output low-z t clz 5?5?5?ns 4 oe# low to output low-z t olz 0?0?0?ns 4 lb# / ub# low to output low-z t blz 0?0?0?ns 4 ce1# high to output high-z t chz ?20?20?20ns 3 oe# high to output high-z t ohz ?20?14?14ns 3 lb# / ub# high to output high-z t bhz ?20?20?20ns 3 address setup time to ce1# low t asc ? 6??6??6?ns address setup time to oe# low t aso 10 ? 10 ? 10 ? ns address invalid time t ax ?10?10?10ns 5, 8 address hold time from ce1# high t chah -6 ? ?6 ? ?6 ? ns 9 address hold time from oe# high t ohah -6 ? ?6 ? ?6 ? ns we# high to oe# low time for read t whol 10 1000 12 ? 25 ? ns 10 ce1# high pulse width t cp 10 ? 12 ? 12 ? ns
108 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information ac characteristics write operation notes: 1. maximum value is applicable if ce1# is kept at low without any address change. if the relaxation is needed by system operation, please contact local spansion representative for the relaxation of 1s limitation. 2. minimum value must be equal or gr eater than the sum of write pulse (t cw , t wp or t bw ) and write recovery time (t wr ). 3. write pulse is defined from high to low transition of ce1#, we#, or lb#/ub#, whichever occurs last. 4. applicable for byte mask only. byte mask setup time is defined to the high to low transition of ce1# or we# whichever occurs last. 5. applicable for byte mask only. byte mask hold time is defi ned from the low to high transi tion of ce1# or we# whichever occurs first. 6. write recovery is defined from low to high transition of ce1#, we#, or lb#/ub#, whichever occurs first. 7. t wph minimum is absolute minimum value for device to de tect high level. and it is defined at minimum v ih level. 8. if oe# is low after minimum t ohcl , read cycle is initiated. in other words, oe # must be brought to high within 5ns after ce1# is brought to low. once read cycle is initia ted, new write pulse should be input after minimum t rc is met. 9. if oe# is low after new address input, read cycle is initiated. in other word, oe# must be brought to high at the same time or before new address valid. once read cycle is init iated, new write pulse should be input after minimum t rc is met and data bus is in high-z. parameter symbol 16m 32m 64m unit notes min. max. min. max. min. max. write cycle time t wc 70 1000 65 1000 65 1000 ns 1,2 address setup time t as 0 ? 0 ? 0 ? ns 3 ce1# write pulse width t cw 45 ? 40 ? 40 ? ns 3 we# write pulse width t wp 45 ? 40 ? 40 ? ns 3 lb#/ub# write pulse width t bw 45 ? 40 ? 40 ? ns 3 lb#/ub# byte mask setup time t bs -5 ? ?5 ? ?5 ? ns 4 lb#/ub# byte mask hold time t bh -5 ? ?5 ? ?5 ? ns 5 write recovery time t wr 0 ? 0 ? 0 ? ns 6 ce1# high pulse width t cp 10 ? 12 ? 12 ? ns we# high pulse width t whp 7.5 1000 7.5 1000 7.5 1000 ns 7 lb#/ub# high pulse width t bhp 10 1000 12 1000 12 1000 ns data setup time t ds 15 ? 12 ? 12 ? ns data hold time t dh 0 ? 0 ? 0 ? ns oe# high to ce1# low setup time for write t ohcl -5 ? ?5 ? ?5 ? ns 8 oe# high to address setup time for write t oes 0 ? 0 ? 0 ? ns 9 lb# and ub# write pulse overlap t bwo 30 ? 30 ? 30 ? ns
february 8, 2005 s71gl064a_00_a2 psram type 7 109 advance information ac characteristics power down parameters notes: 1. applicable also to power-up. 2. applicable when 4mb and 8mb partial modes are programmed. other timing parameters notes: 1. some data might be written into any address location if t chwx (min) is not satisfied. 2. the input transition time (t t ) at ac testing is 5ns as shown in below. if actu al tt is longer than 5ns, it can violate the ac specification of some of the timing parameters. parameter symbol 16m 32m 64m unit note min. max. min. max. min. max. ce2 low setup time for power down entry t csp 10 ? 10 ? 10 ? ns ce2 low hold time after power down entry t c2lp 80 ? 65 ? 65 ? ns ce1# high hold time following ce2 high after power down exit [sleep mode only] t chh 300 ? 300 ? 300 ? s 1 ce1# high hold time following ce2 high after power down exit [not in sleep mode] t chhp n/a 1 ? 1 ? s 2 ce1# high setup time following ce2 high after power down exit t chs 0 ? 0 ? 0 ? ns 1 parameter symbol 16m 32m 64m unit note min. max. min. max. min. max. ce1# high to oe# invalid time for standby entry t chox 10 ? 10 ? 10 ? ns ce1# high to we# invalid time for standby entry t chwx 10 ? 10 ? 10 ? ns 1 ce2 low hold time after power-up t c2lh 50 ? 50 ? 50 ? s ce1# high hold time following ce2 high after power-up t chh 300 ? 300 ? 300 ? s input transition time t t 1 25 1 25 1 25 ns 2
110 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information ac characteristics ac test conditions ac measurement output load circuits figure 37. ac output load circuit ? 16 mb figure 38. ac output load circuit ? 32 mb and 64 mb symbol description te s t s e t u p value unit note v ih input high level v dd * 0.8 v v il input low level v dd * 0.2 v v ref input timing measurement level v dd * 0.5 v t t input transition time between v il and v ih 5 ns device under test v dd v dd *0.5 v v ss out 0.1 f 50 pf 50 ohm device under test v dd v ss out 0.1 f 50pf
february 8, 2005 s71gl064a_00_a2 psram type 7 111 advance information timing diagrams read timings note: this timing diagram assumes ce2=h and we#=h. figure 39. read timing #1 (basic timing) note: this timing diagram assumes ce2=h and we#=h. figure 40. read timing #2 (oe# address access t ce valid data output address ce1# dq (output) oe# t chz t rc t olz t chah t cp address valid t asc t asc t ohz t oh t bhz lb#/ ub# t oe t ba t blz t clz t aa valid data output address ce 1# dq (output) t ohz t oe t rc t olz address valid valid data output address valid t rc t oh t oh oe# t ax low t aa t ohah t aso lb#/ub#
112 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information note: this timing diagram assumes ce2=h and we#=h. figure 41. read timing #3 (lb#/ub# byte access) note: this timing diagram assumes ce2=h and we#=h. figure 42. read timing #4 (page address access after ce1# control access for 32m and 64m only) t aa valid data output address dq1-8 (output) ub# t bhz t ba t rc t blz address valid valid data output t bhz t oh lb# t ax low t ba t ax dq9-16 (output) t blz t ba t blz t oh t bhz t oh valid data output ce1#, oe# valid data output (normal access) a ddress (a2-a0) ce1# dq (output) oe# t chz t ce t rc t clz address valid valid data output (page access) address valid t prc t oh t oh t chah t paa a ddress (a21-a3) address valid t paa t oh t prc t paa t prc t oh address valid address valid t rc t asc lb#/ub#
february 8, 2005 s71gl064a_00_a2 psram type 7 113 advance information notes: 1. this timing diagram assumes ce2=h and we#=h. 2. either or both lb# and ub# must be low when both ce1# and oe# are low. figure 43. read timing #5 (random and page address access for 32m and 64m only) write timings note: this timing diagram assumes ce2=h. figure 44. write timing #1 (basic timing) valid data output (normal access) a ddress (a2-a0) ce 1# dq (output) oe# t oe t rc t olz t blz t aa valid data output (page access) address valid t prc t oh t oh t rc t paa a ddress (a21-a3) address valid t aa t oh address valid t rc t paa t prc t oh address valid address valid t rc t ax t ax t ba address valid low t aso lb#/ub# t as valid data input a ddress ce1# dq (input) we# t dh t ds t wc t wr t wp t cw lb#, ub# t as t bw address valid t as t as t wr oe# t ohcl t as t as t wr t cp t whp t bhp
114 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information note: this timing diagram assumes ce2=h. figure 45. write timing #2 (we# control) note: this timing diagram assumes ce2=h and oe#=h. figure 46. write timing #3-1(we#/lb# /ub# byte write control) t as a ddress we# ce1# t wc t wr t wp lb#, ub# address valid t as t wr t wp valid data input dq (input) t dh t ds oe# t oes t ohz t wc valid data input t dh t ds low address valid t ohah t whp t as a ddress we# ce1# t wc t wr t wp lb# address valid t as t wr t wp valid data input dq1-8 (input) t dh t ds ub# t wc t dh t ds low address valid dq9-16 (input) t bs t bh t bs t bh t whp
february 8, 2005 s71gl064a_00_a2 psram type 7 115 advance information note: this timing diagram assumes ce2=h and oe#=h. figure 47. write timing #3-3 (we#/lb# /ub# byte write control) note: this timing diagram assumes ce2=h and oe#=h. figure 48. write timing #3-4 (we#/lb# /ub# byte write control) t as a ddress we# ce1# t wc t wr t bw lb# address valid t as t wr t bw valid data input dq1-8 (input) t dh t ds ub# t wc valid data input t dh t ds low address valid dq9-16 (input) t bs t bh t bs t bh t whp t as a ddress we# ce1# t wc t wr t bw lb# address valid t as t wr t bw dq1-8 (input) t dh t ds ub# t wc t dh t ds low address valid dq9-16 (input) t dh t ds t as t wr t bw t as t wr t bw t dh t ds valid data input valid data input valid data input valid data input t bwo t bwo t bhp t bhp
116 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information read/write timings notes: 1. this timing diagram assumes ce2=h. 2. write address is valid from either ce1# or we# of last falling edge. figure 49. read/write timing #1-1 (ce1# control) notes: 1. this timing diagram assumes ce2=h. 2. oe# can be fixed low during write operation if it is ce1# controlled write at read-write-read sequence. figure 50. read / write timing #1-2 (ce1#/we#/oe# control) read data output a ddress ce1# dq we# t wc t cw oe# t ohcl ub#, lb# t chah t cp write address t as t rc write data input t ds t chz t oh t cp t ce t asc read address t wr t chah t dh t clz t oh read data output a ddress ce1# dq we# t wc t wp oe# t ohcl ub#, lb# t oe t chah t cp write address t as t rc write data input t ds t chz t oh t cp t ce t asc read address t wr t chah t dh t olz t oh read data output
february 8, 2005 s71gl064a_00_a2 psram type 7 117 advance information notes: 1. this timing diagram assumes ce2=h. 2. ce1# can be tied to low for we# and oe# controlled operation. figure 51. read / write timing #2 (oe#, we# control) notes: 1. this timing diagram assumes ce2=h. 2. ce1# can be tied to low for we# and oe# controlled operation. figure 52. read / write timing #3 (oe#, we#, lb#, ub# control) read data output a ddress ce1# dq we# t wc t wp oe# ub#, lb# t oe write address t as t rc write data input t ds t ohz t oh t aa read address t wr t dh t olz t oh read data output t ohz low t aso t ohah t oes t ohah t whol read data output a ddress ce1# dq we# t wc t bw oe# ub#, lb# t ba write address t as t rc write data input t ds t bhz t oh t aa read address t dh t blz t oh read data output t bhz low t aso t ohah t ohah t oes t whol t wr
118 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information note: the t c2lh specifies after v dd reaches specified minimum level. figure 53. power-up timing #1 note: the t chh specifies after v dd reaches specified minimum level and applicable to both ce1# and ce2. figure 54. power-up timing #2 note: this power down mode can be also used as a reset timi ng if power-up timing abov e could not be satisfied and power-down program was not performed prior to this reset. figure 55. power down entr y and exit timing t c2lh ce1# v dd v dd min 0v ce2 t chh t chs ce1# v dd v dd min 0v ce2 t chh t csp ce1# power down entry ce2 t c2lp t chh (t chhp ) power down mode power down exit t chs dq high-z
february 8, 2005 s71gl064a_00_a2 psram type 7 119 advance information note: both t chox and t chwx define the earliest entry timing for standby mode. if either of timing is not satisfied, it takes t rc (min) period for standby mode from ce1# low to high transition. figure 56. standby entry timing after read or write notes: 1. the all address inputs must be high from cycle #1 to #5. 2. the address key must confirm the format specified in page 104. if not, the operation and data are not guaranteed. 3. after t cp following cycle #6, the power down program is completed and returned to the normal operation. figure 57. power down program timing (for 32m/64m only) t chox ce1# oe# we# active (read) standby active (write) standby t chwx address ce1# dq* 3 we# t rc oe# lb#, ub# rda msb* 1 msb* 1 msb* 1 msb* 1 msb* 1 key* 2 t wc t wc t wc t wc t rc t cp t cp t cp t cp t cp t cp * 3 cycle #1 cycle #2 cycle #3 cycle #4 cycle #5 cycle #6 rda rda x x rdb
120 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information ty p e 1 s r a m 4/8 megabit cmos sram common features ? process technology: full cmos ? power supply voltage: 2.7~3.3v ? three state outputs notes: 1. ub#, lb# swapping is available only at x16. x8 or x16 select by byte# pin. pin description ve r s i o n density organization (i sb1 , max.) standby (i cc2 , max.) operating mode f 4mb x8 or x16 (note 1) 10 a 22 ma dual cs, ub# / lb# (tcs) g 4mb x8 or x16 (note 1) 10 a 22 ma dual cs, ub# / lb# (tcs) c 8mb x8 or x16 (note 1) 15 a 22 ma dual cs, ub# / lb# (tcs) d 8mb x16 tbd tbd dual cs, ub# / lb# (tcs) pin name description i/o cs1#, cs2 chip selects i oe# output enable i we# write enable i byte# word (v cc )/byte (v ss ) select i a0~a17 (4m) a0~a18 (8m) address inputs i sa address input for byte mode i i/o0~i/o15 data inputs/outputs i/o v cc power supply - v ss ground - dnu do not use - nc no connection -
february 8, 2005 s71gl064a_00_a2 type 1 sram 121 advance information functional description 4m version f, 4m version g, 8m version c note: x means don?t care (must be low or high state). byte mode cs1# cs2 oe# we# byte# sa lb# ub# io 0~7 io 8~15 mode power h x x x x x x x high-z high-z deselected standby x l x x x x x x high-z high-z deselected standby x x x x x x h h high-z high-z deselected standby l h h h v cc x l x high-z high-z output disabled active l h h h v cc x x l high-z high-z output disabled active l h l h v cc x l h d out high-z lower byte read active l h l h v cc x h l high-z d out upper byte read active l h l h v cc x l l d out d out word read active l h x l v cc x l h d in high-z lower byte write active l h x l v cc x h l high-z d in upper byte write active l h x l v cc x l l d in d in word write active cs1# cs2 oe# we# byte# sa lb# ub# io 0~7 io 8~15 mode power h x x x x x x x high-z high-z deselected standby x l x x x x x x high-z high-z deselected standby l h h h x x h h high-z high-z deselected standby l h l l v cc x l x high-z high-z output disabled active l h x l v cc x x l high-z high-z output disabled active
122 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information functional description 8m version d note: x means don?t care (must be low or high state). absolute maximum ratings 4m version f stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. functional operation should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for extended periods may affect reliability . 4 m ve r s io n g, 8 m ve r s io n c , 8 m ve r s io n d stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. functional operation should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for extended periods may affect reliability . cs1# cs2 oe# we# lb# ub# io 0~8 io 9~16 mode power h x x x x x high-z high-z deselected standby x l x x x x high-z high-z deselected standby x x x x h h high-z high-z deselected standby l h h h l x high-z high-z output disabled active l h h h x l high-z high-z output disabled active l h l h l h d out high-z lower byte read active l h l h h l high-z d out upper byte read active l h l h l l d out d out word read active l h x l l h d in high-z lower byte write active l h x l h l high-z d in upper byte write active l h x l l l d in d in word write active item symbol ratings unit voltage on any pin relative to v ss v in ,v out -0.2 to v cc +0.3v v voltage on v cc supply relative to v ss v cc -0.2 to 4.0v v power dissipation p d 1.0 w operating temperature t a -40 to 85 c item symbol ratings unit voltage on any pin relative to v ss v in ,v out -0.2 to v cc +0.3v (max. 3.6v) v voltage on v cc supply relative to v ss v cc -0.2 to 3.6v v power dissipation p d 1.0 w operating temperature t a -40 to 85 c
february 8, 2005 s71gl064a_00_a2 type 1 sram 123 advance information dc characteristics recommended dc operating conditions (note 1) notes: 1. t a = -40 to 85 c, unless otherwise specified. 2. overshoot: vcc+1.0v in case of pulse width 20ns. 3. undershoot: -1.0v in case of pulse width 20ns. 4. overshoot and undershoot are sampled, not 100% tested. capacitance (f=1mhz, t a =25 c) note: capacitance is sampled, not 100% tested dc operating characteristics common item symbol min ty p max unit supply voltage v cc 2.7 3.0 3.3 v ground v ss 0 0 0 v input high voltage v ih 2.2 - v cc +0.2 (note 2) v input low voltage v il -0.2 (note 3) - 0.6 v item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 10 pf item symbol test conditions min ty p (note) max unit input leakage current i li v in =v ss to v cc -1 - 1 a output leakage current i lo cs1#=v ih or cs2=v il or oe#=v ih or we#=v il or lb#=ub#=v ih , v io =v ss to v cc -1 - 1 a output low voltage v ol i ol = 2.1ma - - 0.4 v output high voltage v oh i oh = -1.0ma 2.4 - - v
124 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information 4m version f note: typical values are not 100% tested. 4m version g note: typical values are not 100% tested. item symbol test conditions min ty p (note) max unit average operating current i cc1 cycle time=1s, 100% duty, i io =0ma, cs1# 0.2v, cs2 v cc -0.2v, byte#=v ss or v cc , v in 0.2v or v in vcc-0.2v, lb# 0.2v or/and ub# 0.2v - - 3 ma i cc2 cycle time=min, i io =0ma, 100% duty, cs1# = v il , cs2=v ih , byte# = v ss or v cc , v in =v il or v ih , lb# 0.2v or/ and ub# 0.2v - - 22 ma standby current (cmos) i sb1 (note) cs1# v cc -0.2v, cs2 v cc -0.2v (cs1# controlled) or cs2 0.2v (cs2 controlled), byte# = v ss or v cc , other input =0~v cc - 1.0 (note) 10 a item symbol test conditions min ty p (note) max unit average operating current i cc1 cycle time=1s, 100% duty, i io =0ma, cs1# 0.2v, cs2 v cc -0.2v, byte#=v ss or v cc , v in 0.2v or v in vcc-0.2v, lb# 0.2v or/and ub# 0.2v - - 4 ma i cc2 cycle time=min, i io =0ma, 100% duty, cs1# = v il , cs2=v ih , byte# = v ss or v cc , v in =v il or v ih , lb# 0.2v or/ and ub# 0.2v - - 22 ma standby current (cmos) i sb1 (note) cs1# v cc -0.2v, cs2 v cc -0.2v (cs1# controlled) or cs2 0.2v (cs2 controlled), byte# = v ss or v cc , other input = 0~v cc - 3.0 (note) 10 a
february 8, 2005 s71gl064a_00_a2 type 1 sram 125 advance information 8m version c note: typical values are not 100% tested. 8m version d note: typical values are not 100% tested. item symbol test conditions min ty p (note) max unit average operating current i cc1 cycle time=1s, 100% duty, i io =0ma, cs1# 0.2v, cs2 v cc -0.2v, byte#=v ss or v cc , v in 0.2v or v in vcc-0.2v, lb# 0.2v or/and ub# 0.2v - - 3 ma i cc2 cycle time=min, i io =0ma, 100% duty, cs1# = v il , cs2=v ih , byte# = v ss or v cc , v in =v il or v ih , lb# 0.2v or/ and ub# 0.2v - - 22 ma standby current (cmos) i sb1 (note) cs1# v cc -0.2v, cs2 v cc -0.2v (cs1# controlled) or cs2 0.2v (cs2 controlled), byte# = v ss or v cc , other input = 0~v cc - - 15 a item symbol test conditions min ty p (note) max unit average operating current i cc1 cycle time=1s, 100% duty, i io =0ma, cs1# 0.2v, cs2 v cc -0.2v, byte#=v ss or v cc , v in 0.2v or v in vcc-0.2v, lb# 0.2v or/and ub# 0.2v - - tbd ma i cc2 cycle time=min, i io =0ma, 100% duty, cs1# = v il , cs2=v ih , byte# = v ss or v cc , v in =v il or v ih , lb# 0.2v or/ and ub# 0.2v - - tbd ma standby current (cmos) i sb1 (note) cs1# v cc -0.2v, cs2 v cc -0.2v (cs1# controlled) or cs2 0.2v (cs2 controlled), byte# = v ss or v cc , other input = 0~v cc - - tbd a
126 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information ac operating conditions test conditions test load and test input/output reference ? input pulse level: 0.4 to 2.2v ? input rising and falling time: 5ns ? input and output reference voltage: 1.5v ? output load (see figure 58): cl= 30pf+1ttl notes: 1. including scope and jig capacitance. 2. r1=3070 ? , r2=3150 ?. 3. v tm =2.8v. ac characteristics figure 58. ac output load ta b l e 3 3 . read/write characteristics (v cc =2.7-3.3v) parameter list symbol speed bins units 70ns min max read read cycle time t rc 70 - ns address access time t aa - 70 ns chip select to output t co1 , t co2 - 70 ns output enable to valid output t oe - 35 ns lb#, ub# access time t ba - 70 ns chip select to low-z output t lz1 , t lz2 10 - ns lb#, ub# enable to low-z output t blz 10 - ns output enable to low-z output t olz 5 - ns chip disable to high-z output t hz1 , t hz2 0 25 ns ub#, lb# disable to high-z output t bhz 0 25 ns output disable to high-z output t ohz 0 25 ns output hold from address change t oh 10 - ns v tm (note 3) r1 (note 2) cl (note 1) r2 (note 2)
february 8, 2005 s71gl064a_00_a2 type 1 sram 127 advance information data retention characteristics 4m version f notes: 1. cs1 controlled:cs1# v cc -0.2v. cs2 controlled: cs2 0.2v. 2. typical values are not 100% tested. write write cycle time t wc 70 - ns chip select to end of write t cw 60 - ns address set-up time t as 0 - ns address valid to end of write t aw 60 - ns lb#, ub# valid to end of write t bw 60 - ns write pulse width t wp 50 - ns write recovery time t wr 0 - ns write to output high-z t whz 0 20 ns data to write time overlap t dw 30 - ns data hold from write time t dh 0 - ns end write to output low-z t ow 5 - ns item symbol test condition min ty p max unit v cc for data retention v dr cs1# v cc -0.2v (note 1) , v in 0v. byte# = v ss or v cc 1.5 - 3.3 v data retention current i dr v cc =3.0v, cs1# v cc -0.2v (note 1) , v in 0v - 1.0 (note 2) 10 a data retention set-up time t sdr see data retention waveform 0 - - ns recovery time t rdr t rc - - table 33. read/write characteristics (v cc =2.7-3.3v) (continued) parameter list symbol speed bins units 70ns min max
128 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information 4m version g notes: 1. cs1 controlled:cs1# v cc -0.2v. cs2 controlled: cs2 0.2v. 8m version c notes: 1. cs1 controlled:cs1# v cc -0.2v. cs2 controlled: cs2 0.2v. 8m version d notes: 1. cs1 controlled:cs1# v cc -0.2v. cs2 controlled: cs2 0.2v. timing diagrams item symbol test condition min ty p max unit v cc for data retention v dr cs1# v cc -0.2v (note 1) , v in 0v. byte# = v ss or v cc 1.5 - 3.3 v data retention current i dr v cc =1.5v, cs1# v cc -0.2v (note 1) , v in 0v - - 3 a data retention set-up time t sdr see data retention waveform 0 - - ns recovery time t rdr t rc - - item symbol test condition min ty p max unit v cc for data retention v dr cs1# v cc -0.2v (note 1) . byte# = v ss or v cc 1.5 - 3.3 v data retention current i dr v cc =3.0v, cs1# v cc -0.2v (note 1) - - 15 a data retention set-up time t sdr see data retention waveform 0 - - ns recovery time t rdr t rc - - item symbol test condition min ty p max unit v cc for data retention v dr cs1# v cc -0.2v (note 1) , byte# = v ss or v cc 1.5 - 3.3 v data retention current i dr v cc =3.0v, cs1# v cc -0.2v (note 1) - - tbd a data retention set-up time t sdr see data retention waveform 0 - - ns recovery time t rdr t rc - - figure 59. timing waveform of read cycle(1) (address controlled, cs#1=oe#=v il , cs2=we#=v ih , ub# and/or lb#=v il ) t aa t rc t oh address data out previous data valid data valid
february 8, 2005 s71gl064a_00_a2 type 1 sram 129 advance information notes: 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. figure 60. timing waveform of read cycle(2) (we#=v ih , if byte# is low, ignore ub#/lb# timing) figure 61. timing waveform of write cycle(1) (we# controlled, if byte# is low, ignore ub#/lb# timing) high-z t rc t oh t aa t co1 t ba t oe t olz t blz t lz t ohz t bhz t hz t co2 address cs1# cs2 ub#, lb# oe# data out data valid t wc t cw(2) t wr(4) t aw t bw t wp(1) t as(3) t dh t dw t whz t ow high-z high-z t cw(2) address cs1# cs2 ub#, lb# we# data in data out data undefined data valid
130 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information figure 62. timing waveform of write cycle(2) (cs# controlled, if byte# is low, ignore ub#/lb# timing) notes: 1. a write occurs during the overlap (t wp ) of low cs1# and low we#. a write begins when cs1# goes low and we# goes low with asserting ub# or lb# for single byte oper ation or simultaneously asse rting ub# and lb# for double byte operation. a write ends at th e earliest transition when cs1# goes high and we# goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs1# going low to the end of write. 3. t as is measured from th e address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr applied in case a write ends as cs1# or we# going high. figure 63. timing waveform of write cycle(3) (ub#, lb# controlled) high-z high-z t wc t cw(2) t aw t bw t wp(1) t dh t dw t wr(4) t as(3) address cs1# cs2 ub#, lb# we# data in data out data valid high-z high-z t wc t cw(2) t bw t wp(1) t dh t dw t wr(4) t aw t as(3) t cw(2) address cs1# cs2 ub#, lb# we# data in data out data valid
february 8, 2005 s71gl064a_00_a2 type 1 sram 131 advance information figure 64. data retention waveform t sdr t rdr t sdr t rdr v cc 2.7v 2.2v v dr cs1# gnd cs1# controlled cs2 controlled v cc 2.7v v dr 0.4v gnd cs2 cs1# v cc - 0.2v data retention mode data retention mode cs2 0.2v
132 s71gl064a based mcps s71gl064a_00_a2 february 8, 2005 advance information revision summary revision a (october 28, 2004) initial release. revision a1 (december 7, 2004) global access speed updated. mcp block diagram control signals updated. pin description descriptions updated. ordering information package modifiers and psram densities updated. valid combinations table speed options updated. revision a2 (february 8, 2005) psram type 7 entire section updated. colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and househol d use, but are not designed, developed and manufactured as contem plated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and c ould lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear re action control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon sy stem), or (2) for any use where chance of failure is intolerabl e ( i.e., submersible repeater and artificial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages ari sing in connection with above-men - tioned uses of the products. any semiconductor devices have an in herent chance of failure. you must protect against injury, dam age or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain re strictions on export under the foreign exchange and foreign trade law of japan, the us export administration regula tions or the applicable laws of any oth er country, the prior au - thorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without noti ce. this document may contain information on a spansion llc pro duct under development by spansion llc. spansion llc reserves the right to change or discontinue work on any product without notice. the information i n this document is provided as is without warranty or guarantee of any kind as to its ac curacy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion llc assu mes no liability for any damages of any kind arising out of the use of the informatio n in this document. copyright ?2004-2005 spansion llc. all rights reserved. spansion, the spansion logo, and mirrorbit are trademarks of spansion l lc. other company and product names used in this publication are for identification purpo ses only and may be trademarks of their respective companies .

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